Semiconductor structures providing electrical isolation

Abstract

Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“L effective ”) and a field gate oxide. Semiconductor structures formed by these methods are also disclosed.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 isolation oxide regions in a substrate, each isolation oxide region adjacent on a first side to a first gate and adjacent on a second side to a second gate, each isolation oxide region having a greater depth into the substrate than a depth of each of the first gate and the second gate.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the first side of the isolation oxide region and the second side of the isolation oxide region are opposing sidewalls of the isolation oxide region. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the entire isolation oxide region is in the substrate. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein each of the isolation oxide regions has a uniform width along a length of the isolation oxide region. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the first side of the isolation oxide region is laterally adjacent to the first gate and the second side of the isolation oxide regions is laterally adjacent to the second gate. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein a single isolation oxide region is positioned between the first gate and the second gate. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising a liner adjacent the first gate and the second gate. 
     
     
         8 . The semiconductor structure of  claim 7 , further comprising a gate oxide adjacent the first gate and the second gate. 
     
     
         9 . The semiconductor structure of  claim 8 , wherein a sidewall of the first gate is in direct contact with the liner and an opposing sidewall of the first gate is in direct contact with the gate oxide. 
     
     
         10 . A semiconductor structure, comprising:
 a pair of gates and an isolation oxide region interposed between a pair of fins of a substrate, each gate of the pair of gates having a vertical sidewall adjacent to a vertical sidewall of the isolation oxide region and an opposing vertical sidewall adjacent to a vertical sidewall of a fin of the pair of fins, and each isolation oxide region extending farther into the substrate than the gates of the pair of gates.   
     
     
         11 . The semiconductor structure of  claim 10 , wherein the isolation oxide region is interposed between the gates of the pair of gates, and the pair of gates are interposed between the fins of the pair of fins. 
     
     
         12 . The semiconductor structure of  claim 10 , wherein an upper surface of the fins is coplanar with an upper surface of the isolation oxide region. 
     
     
         13 . The semiconductor structure of  claim 10 , wherein adjacent fins are isolated from one another by the isolation oxide regions. 
     
     
         14 . The semiconductor structure of  claim 10 , wherein each fin of the pair of fins has a width of a minimum feature size F. 
     
     
         15 . The semiconductor structure of  claim 10 , wherein each gate of the pair of gates has a width of a half of a minimum feature size F (F/2). 
     
     
         16 . The semiconductor structure of  claim 10 , wherein a first sidewall of each gate is in direct contact with a liner and a second sidewall of each gate is in direct contact with a gate oxide. 
     
     
         17 . A semiconductor structure, comprising:
 isolation oxide regions in a substrate, each of the isolation oxide regions comprising a uniform width along a length of the isolation oxide region, a first side of the isolation oxide region adjacent to a first gate within the substrate, a second side of the isolation oxide region adjacent to a second gate within the substrate, and the isolation oxide region extending deeper into the substrate than the first gate and the second gate.   
     
     
         18 . The semiconductor structure of  claim 17 , further comprising fins adjacent to the first gate and the second gate. 
     
     
         19 . The semiconductor structure of  claim 18 , wherein an upper surface of the isolation oxide regions is coplanar with an upper surface of the fins. 
     
     
         20 . The semiconductor structure of  claim 17 , wherein an upper surface of each of the first gate and the second gate is recessed below an upper surface of the isolation oxide regions.