Stacked carbon-based fets

Abstract

A stacked transistor device includes a lower transistor that has a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer. The lower source and drain regions are in electrical contact with respective conductive source and drain extensions formed in the substrate. An upper transistor has upper source and drain regions vertically aligned with the respective lower source and drain regions. The upper source and drain regions are separated from the respective lower source and drain regions by an insulator. The upper transistor further includes an upper channel layer formed over the upper source and drain regions.

What is claimed is: 
     
         1 . A stacked transistor device, comprising:
 a lower transistor, comprising a lower channel layer formed on a substrate and lower source and drain regions formed directly over the lower channel layer and in electrical contact with respective conductive source and drain extensions formed in the substrate; and   an upper transistor, comprising upper source and drain regions vertically aligned with the respective lower source and drain regions and separated from said respective lower source and drain regions by an insulator and further comprising an upper channel layer formed over the upper source and drain regions.   
     
     
         2 . The stacked transistor device of  claim 1 , wherein the upper and lower channel layers are carbon-based. 
     
     
         3 . The stacked transistor device of  claim 1 , wherein the upper channel layer is carbon-based and the lower channel layer is silicon based. 
     
     
         4 . The stacked transistor device of  claim 1 , wherein the lower transistor comprises a lower gate region and wherein the upper transistor comprises an upper gate region 
     
     
         5 . The stacked transistor device of  claim 1 , further comprising:
 a lower gate dielectric layer formed on the lower channel layer; and   an upper gate dielectric layer formed over the upper source and drain regions.   
     
     
         6 . The stacked transistor device of  claim 1 , further comprising at least one conductive metal contact that extends from above the upper channel layer and contacts a source or drain extension. 
     
     
         7 . The stacked transistor device of  claim 6 , wherein the at least one conductive metal contact passes through an opening in the lower channel layer. 
     
     
         8 . The stacked transistor device of  claim 6 , wherein a conductive metal surface contact is in contact with both source regions or both drain regions to form a dual-transistor device. 
     
     
         9 . The stacked transistor device of  claim 8 , wherein the conductive metal surface contact connects to both drain regions to form an inverter. 
     
     
         10 . The stacked transistor device of  claim 1 , wherein at least one conductive metal contact that passes through an opening in the upper channel layer. 
     
     
         11 . The stacked transistor device of  claim 1 , wherein at least one conductive metal contact is formed contiguously and from a same material as an upper source or drain region and passes through an opening in a respective insulator to contact a respective lower source or drain region. 
     
     
         12 . The stacked transistor device of  claim 1 , wherein an upper source region and an upper drain region are each formed entirely from metal. 
     
     
         13 . The stacked transistor device of  claim 1 , wherein an upper gate region material has a different work function from a lower gate region material, such that the gate regions will not interfere with one another in operation.