Data processing system having end-to-end error correction and method therefor

Abstract

In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.

What is claimed is: 
     
         1 . In a data processing system having a processor and a memory coupled to the processor via a system interconnect, a method comprising:
 initiating a read operation of a memory location;   in response to the initiating the read operation, receiving a first data value and a first checkbit value corresponding to the first data value from the memory location, wherein the first data value comprises a first data value portion and a second data value portion, each of the first and second data value portions having fewer bits than the first data value;   providing the first checkbit value to first transforming circuitry and to second transforming circuitry, wherein the first transforming circuitry generates a second checkbit value corresponding to the first data value portion and the second transforming circuitry generates a third checkbit value corresponding to the second data value portion; and   storing the first data value portion with the second checkbit value in a first storage location and storing the second data value portion with the third checkbit value in a second storage location.   
     
     
         2 . The method of  claim 1 , further comprising:
 accessing the first data value portion and the second checkbit value; and   using the second checkbit value and not the first checkbit value to check the first data value portion.   
     
     
         3 . The method of  claim 1 , further comprising:
 in response to the step of initiating the read operation, the memory providing the first data value and the second checkbit value to the processor via the system interconnect; and   after the step of receiving the first data value and the second checkbit value and prior to the step of providing the first checking value to the first transforming circuitry and the second transforming circuitry, performing, by the processor, end to end error detection by using the first checkbit value to check the first data value.   
     
     
         4 . The method of  claim 1 , wherein each of the first and second storage locations are located within a cache memory of the processor and the memory location is located in the memory, and wherein the step of initiating the read operation is performed in response to a cache miss or a cache fill. 
     
     
         5 . The method of  claim 4 , wherein:
 the first transforming circuitry uses system error coding function circuitry for generating a checkbit value for an N-bit data value, first internal error coding function circuitry for generating a checkbit value for an M-bit data value, and cache index error coding function circuitry for generating a checkbit value for a cache index of the cache;   the second transforming circuitry uses the system error coding function circuitry, second internal error coding function circuitry for generating a checkbit value for the M-bit data value, and the cache index error coding function circuitry; and   the second internal error coding function circuitry implements a different coding function than the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being the M-bit data value.   
     
     
         6 . The method of  claim 1 , wherein:
 the first transforming circuitry uses system error coding function circuitry for generating a checkbit value for an N-bit data value and first internal error coding function circuitry for generating a checkbit value for an M-bit data value;   the second transforming circuitry uses the system error coding function circuitry and second internal error coding function circuitry for generating a checkbit value for an M-bit data value; and   the second internal error coding function circuitry implements a different coding function that the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being an M-bit data value.   
     
     
         7 . The method of  claim 6 , wherein:
 the system error coding function circuitry comprises a first plurality of exclusive OR (XOR) gates, wherein each XOR gate of the first plurality of XOR gates outputs one corresponding bit value of the first checkbit value, and wherein each XOR gate of the first plurality of XOR gates receives a predetermined subset of bit values of the first data value;   the first internal error coding function circuitry comprises a second plurality of XOR gates, wherein each XOR gate of the second plurality of XOR gates outputs one corresponding bit value of the third checkbit value, and wherein each XOR gate of the second plurality of XOR gates receives a predetermined subset of bit values of the second data value portion; and   the second internal error coding function circuitry comprises a third plurality of XOR gates, wherein each XOR gate of the third plurality of XOR gates outputs one corresponding bit value of the second checkbit value, and wherein each XOR gate of the third plurality of XOR gates receives a predetermined subset of bit values of the first data value portion.   
     
     
         8 . A data processing system comprising:
 a memory to store a first data value in a memory location, and a first checkbit value corresponding to the first data value from the memory location;   a processor configured to be in communication with the memory via a system interconnect, the processor to initiate a read operation of the memory location, in response to the read operation being initiated, to receive the first data value and the first checkbit value, wherein the first data value comprises a first data value portion and a second data value portion, each of the first and second data value portions having fewer bits than the first data value;   first transforming circuitry configured to be in communication with the processor, the first transforming circuitry to receive the first checkbit value from the processor, and to generate a second checkbit value corresponding to the first data value portion; and   second transforming circuitry configured to be in communication with the processor, the second transforming circuitry to receive the first checkbit value from the processor, and to generate a third checkbit value corresponding to the second data value portion,   the processor to store the first data value portion with the second checkbit value in a first storage location, and to store the second data value portion with the third checkbit value in a second storage location.   
     
     
         9 . The data processing system of  claim 8 , the processor further to access the first data value portion and the second checkbit value, and use the second checkbit value and not the first checkbit value to check the first data value portion. 
     
     
         10 . The data processing system of  claim 8 , wherein after the processor receives the first data value and the second checkbit value from the memory and prior to when the processor provides the first checking value to the first transforming circuitry and the second transforming circuitry, the processor to perform end to end error detection by using the first checkbit value to check the first data value. 
     
     
         11 . The data processing system of  claim 8 , wherein the processor initiates the read operation in response to a cache miss or a cache fill. 
     
     
         12 . The data processing system of  claim 11 , wherein the first transforming circuitry comprises:
 system error coding function circuitry to generate a checkbit value for an N-bit data value;   first internal error coding function circuitry to generate a checkbit value for an M-bit data value; and   cache index error coding function circuitry to generate a checkbit value for a cache index of the cache;   
     
     
         13 . The data processing system of  claim 12 , wherein the second transforming circuitry comprises:
 second internal error coding function circuitry to generate a checkbit value for the M-bit data value, and wherein the second internal error coding function circuitry implements a different coding function than the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being the M-bit data value.   
     
     
         14 . The data processing system of  claim 8 , wherein the first transforming circuitry comprises:
 system error coding function circuitry to generate a checkbit value for an N-bit data value; and   first internal error coding function circuitry to generate a checkbit value for an M-bit data value;   
     
     
         15 . The data processing system of  claim 14 , wherein the second transforming circuitry comprises:
 the system error coding function circuitry and second internal error coding function circuitry to generate a checkbit value for an M-bit data value, wherein the second internal error coding function circuitry implements a different coding function than the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being an M-bit data value.   
     
     
         16 . The data processing system of  claim 1 , wherein:
 the system error coding function circuitry comprises a first plurality of exclusive OR (XOR) gates, wherein each XOR gate of the first plurality of XOR gates outputs one corresponding bit value of the first checkbit value, and wherein each XOR gate of the first plurality of XOR gates receives a predetermined subset of bit values of the first data value;   the first internal error coding function circuitry comprises a second plurality of XOR gates, wherein each XOR gate of the second plurality of XOR gates outputs one corresponding bit value of the third checkbit value, and wherein each XOR gate of the second plurality of XOR gates receives a predetermined subset of bit values of the second data value portion; and   the second internal error coding function circuitry comprises a third plurality of XOR gates, wherein each XOR gate of the third plurality of XOR gates outputs one corresponding bit value of the second checkbit value, and wherein each XOR gate of the third plurality of XOR gates receives a predetermined subset of bit values of the first data value portion.   
     
     
         17 . In a data processing system having a processor and a memory coupled to the processor via a system interconnect, a method comprising:
 in response to a cache miss or a cache fill, receiving a first data value and a first checkbit value corresponding to the first data value from the memory location, wherein the first data value comprises a first data value portion and a second data value portion;   providing the first checkbit value to first transforming circuitry and to second transforming circuitry, wherein the first transforming circuitry generates a second checkbit value corresponding to the first data value portion and the second transforming circuitry generates a third checkbit value corresponding to the second data value portion;   storing the first data value portion with the second checkbit value in a first storage location of a cache memory of the processor; and   storing the second data value portion with the third checkbit value in a second storage location of the cache memory of the processor.   
     
     
         18 . The method of  claim 17 , further comprising:
 accessing the first data value portion and the second checkbit value; and   using the second checkbit value and not the first checkbit value to check the first data value portion.   
     
     
         19 . The method of  claim 17 , wherein:
 the first transforming circuitry uses system error coding function circuitry for generating a checkbit value for an N-bit data value and first internal error coding function circuitry for generating a checkbit value for an M-bit data value;   the second transforming circuitry uses the system error coding function circuitry and second internal error coding function circuitry for generating a checkbit value for an M-bit data value; and   the second internal error coding function circuitry implements a different coding function that the first internal error coding function and N is greater than M, the first data value being an N-bit data value and each of the first and second data value portions being an M-bit data value.   
     
     
         20 . The method of  claim 19 , wherein:
 the system error coding function circuitry comprises a first plurality of exclusive OR (XOR) gates, wherein each XOR gate of the first plurality of XOR gates outputs one corresponding bit value of the first checkbit value, and wherein each XOR gate of the first plurality of XOR gates receives a predetermined subset of bit values of the first data value;   the first internal error coding function circuitry comprises a second plurality of XOR gates, wherein each XOR gate of the second plurality of XOR gates outputs one corresponding bit value of the third checkbit value, and wherein each XOR gate of the second plurality of XOR gates receives a predetermined subset of bit values of the second data value portion; and   the second internal error coding function circuitry comprises a third plurality of XOR gates, wherein each XOR gate of the third plurality of XOR gates outputs one corresponding bit value of the second checkbit value, and wherein each XOR gate of the third plurality of XOR gates receives a predetermined subset of bit values of the first data value portion.