Schottky Barriers for Resistive Random Access Memory Cells

Abstract

Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through the variable resistance layer in one direction and the other barrier limiting a current in the opposite direction. This combination of the two Schottky barriers provides current compliance during set operations and limits undesirable current overshoots during reset operations. The Schottky barriers' heights are configured to match the resistive switching characteristics of the cell. Conductive layers of the ReRAM cells operable as electrodes may be used to form these Schottky barriers together with semiconductor layers. These semiconductor layers may be different components from a variable resistance layer and, in some embodiments, may be separated by intermediate conductive layers from the variable resistance layers.

What is claimed: 
     
         1 . A resistive random access memory (ReRAM) cell comprising:
 a first conductive layer;   a second conductive layer;   a variable resistance layer between the first conductive layer and the second conductive layer;   a first semiconductor layer between the first conductive layer and the variable resistance layer; and   a second semiconductor layer between the second conductive layer and the variable resistance layer,
 wherein the first conductive layer and the second conductive layer are operable as electrodes; 
 wherein the first semiconductor layer and the first conductive layer form a first Schottky barrier; 
 wherein the second semiconductor layer and the second conductive layer form a second Schottky barrier; 
 wherein the first Schottky barrier is operable to limit an electrical current from the first conductive layer to the second conductive layer, and 
 wherein the second Schottky barrier is operable to limit an electrical current from the second conductive layer to the first conductive layer. 
   
     
     
         2 . The ReRAM cell of  claim 1 , wherein the first semiconductor layer directly interfaces the variable resistance layer. 
     
     
         3 . The ReRAM cell of  claim 2 , wherein the second semiconductor layer directly interfaces the variable resistance layer. 
     
     
         4 . The ReRAM cell of  claim 1 , further comprising a first intermediate conductive layer disposed between the first semiconductor layer and the variable resistance layer. 
     
     
         5 . The ReRAM cell of  claim 4 , further comprising a second intermediate conductive layer disposed between the second semiconductor layer and the variable resistance layer. 
     
     
         6 . The ReRAM cell of  claim 4 , wherein the first semiconductor layer directly interfaces the variable resistance layer. 
     
     
         7 . The ReRAM cell of  claim 1 , wherein the first conductive layer comprising one of aluminum, copper, gold, silver, nickel, palladium, platinum, chromium, molybdenum, tungsten, titanium, or indium. 
     
     
         8 . The ReRAM cell of  claim 1 , wherein the first semiconductor layer comprises one of silicon, a silicon containing compound, germanium, a germanium containing compound, an aluminum containing compound, a boron containing compound, a gallium containing compound, an indium containing compound, a cadmium containing compound, a zinc containing compound, a lead containing compound, or a tin containing compound. 
     
     
         9 . The ReRAM cell of  claim 1 , wherein the first semiconductor layer comprises gallium arsenide or gallium phosphide. 
     
     
         10 . The ReRAM cell of  claim 1 , wherein the first semiconductor layer comprises crystalline silicon and wherein at least a portion of the first semiconductor layer is doped with one of phosphorus, boron, or arsenic. 
     
     
         11 . The ReRAM cell of  claim 1 , wherein the ReRAM cell is a bi-polar cell. 
     
     
         12 . The ReRAM cell of  claim 11 , wherein the first Schottky barrier is operable to pass a set electrical current flowing from the first conductive layer to the second conductive layer when a set voltage is applied between the first conductive layer and the second conductive layer. 
     
     
         13 . The ReRAM cell of  claim 12 , wherein the second Schottky barrier is operable to pass a reset electrical current flowing from the second conductive layer to the first conductive layer when a reset voltage is applied between the first conductive layer and the second conductive layer. 
     
     
         14 . The ReRAM cell of  claim 11 , wherein the first Schottky barrier has a same current limiting characteristic as the second Schottky barrier. 
     
     
         15 . The ReRAM cell of  claim 11 , wherein the first Schottky barrier has a different current limiting characteristic than the second Schottky barrier. 
     
     
         16 . The ReRAM cell of  claim 1 , wherein the variable resistance layer has a variable composition in a direction from the first conductive layer to the second conductive layer. 
     
     
         17 . The ReRAM cell of  claim 1 , wherein the variable resistance layer comprises one of silicon oxide, aluminum oxide, hafnium oxide, or zirconium oxide. 
     
     
         18 . The ReRAM cell of  claim 17 , wherein a concentration of oxygen is less at a surface of the variable resistance layer facing toward the first conductive layer than at a surface of the variable resistance layer facing toward the second conductive layer. 
     
     
         19 . The ReRAM cell of  claim 1 , wherein the first Schottky barrier and the second Schottky barrier retain current limiting characteristics after annealing at 600° C. for 1 minute. 
     
     
         20 . A method of fabricating a resistive random access memory (ReRAM) cell, the method comprising:
 forming a first conductive layer;   forming a first semiconductor layer over the first conductive layer;   forming a variable resistance layer over the first semiconductor layer;   forming a second semiconductor layer over the variable resistance layer; and   forming a second conductive layer over the second semiconductor layer,
 wherein the first conductive layer and the second conductive layer are operable as electrodes, 
 wherein the first semiconductor layer and the first conductive layer form a first Schottky barrier; and 
 wherein the second semiconductor layer and the second conductive layer form a second Schottky barrier.