Thin film transistor and display device using the same

Abstract

There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.

What is claimed is: 
     
         1 . A bottom gate channel etched thin film transistor using an oxide semiconductor layer for a channel layer, the thin film transistor comprising:
 a substrate; a gate electrode interconnection formed on the substrate; a gate insulating film formed on the gate electrode interconnection; and an oxide semiconductor layer to be a channel layer formed on the gate insulating film;   a stacked film of a source electrode interconnection formed to extend above one end of the oxide semiconductor layer and a first hard mask layer for processing the source electrode interconnection;   a stacked film of a drain electrode interconnection formed to extend above the other end of the oxide semiconductor layer and a second hard mask layer for processing the drain electrode interconnection; and   a protective insulating film formed to cover a top face of the first hard mask layer, a side face of the source electrode interconnection, a top face of the oxide semiconductor layer, a top face of the second hard mask layer, and a side face of the drain electrode interconnection.   
     
     
         2 . The thin film transistor according to  claim 1 ,
 wherein a thickness of the protective insulating film on the oxide semiconductor layer is thinner than a total thickness of the first hard mask layer formed above the source electrode interconnection and the protective insulating film.   
     
     
         3 . The thin film transistor according to  claim 1 ,
 wherein in the protective insulating film, a discharge amount of hydrogen molecules is 5×10 21  molecules/cm 3  or less and a discharge amount of water molecules is 3×10 21  molecules/cm 3  or less in TDS analysis.   
     
     
         4 . The thin film transistor according to  claim 1 ,
 wherein a contact layer is formed between the oxide semiconductor layer and the source electrode interconnection and between the oxide semiconductor layer and the drain electrode interconnection.   
     
     
         5 . The thin film transistor according to  claim 4 ,
 wherein an antireflective layer is formed between the source electrode interconnection and the first hard mask layer and between the drain electrode interconnection and the second hard mask layer.   
     
     
         6 . The thin film transistor according to  claim 1 ,
 wherein end portions of the first hard mask layer and the second hard mask layer have a normal tapered angle ranging from an angel of 30 to 70°.   
     
     
         7 . The thin film transistor according to  claim 1 ,
 wherein the source electrode interconnection and the drain electrode interconnection are formed of an Al-based metal.   
     
     
         8 . The thin film transistor according to  claim 1 ,
 wherein the first and the second hard mask layers are formed of SiO, SiN, SiON, MoW, or TiN.   
     
     
         9 . A display device comprising a display region and a drive circuit unit,
 wherein the thin film transistor according to  claim 1  is disposed on the display region; and   an organic planarization film is formed on the protective insulating film.   
     
     
         10 . The display device according to  claim 9 ,
 wherein the display region includes liquid crystal and a color filter.   
     
     
         11 . The display device according to  claim 9 ,
 wherein the display region includes a light emitting layer and a charge transport layer.   
     
     
         12 . A bottom gate channel etched thin film transistor using an oxide semiconductor layer for a channel layer, the thin film transistor being manufactured in the steps of:
 forming an Al-based metal film on a substrate including a gate electrode interconnection, a gate insulating film covering the gate electrode interconnection, and an oxide semiconductor layer to be a channel layer formed on the gate electrode interconnection through the gate insulating film;   forming a hard mask film on the Al-based metal film;   forming a resist pattern having a pattern for forming a source electrode interconnection and a drain electrode interconnection on the hard mask film;   forming a first hard mask layer corresponding to a source electrode interconnection pattern for etching the hard mask film using the resist pattern for a mask and a second hard mask layer corresponding to a drain electrode interconnection pattern;   first ashing for removing the resist pattern;   dry etching the Al-based metal film using the first hard mask layer and the second hard mask layer for masks with a chlorine gas, forming the source electrode interconnection and the drain electrode interconnection, and exposing the oxide semiconductor layer;   second ashing for removing a residual chlorine gas component after the dry etching; and   forming a protective insulating film so as to cover a side wall of the source electrode interconnection, a surface of the oxide semiconductor layer, and a side wall of the drain electrode interconnection.   
     
     
         13 . The thin film transistor according to  claim 12 ,
 wherein the protective insulating film is formed using an SiH 4  gas and an N 2 O gas at a substrate temperature in a range of a temperature of 150° C. to 300° C.   
     
     
         14 . The thin film transistor according to  claim 12 ,
 wherein the ashing after the dry etching is performed in a condition relaxed more than in the ashing for the resist pattern.