Circuit technique to electrically characterize block mask shifts

Abstract

A physical test integrated circuit has a plurality of repeating circuit portions corresponding to an integrated circuit design. A first of the portions is fabricated with a nominal block mask location, and additional ones of the portions are deliberately fabricated with predetermined progressive increased offset of the block mask location from the nominal block mask location. For each of the portions, the difference in threshold voltage between a first field effect transistor and a second field effect transistor is determined. The predetermined progressive increased offset of the block mask location is in a direction from the first field effect transistor to the second field effect transistor. The block mask overlay tolerance is determined at a value of the progressive increased offset corresponding to an inflection of the difference in threshold voltage from a zero difference. A method for on-chip monitoring, and corresponding circuits, are also disclosed.

What is claimed is: 
     
         1 . A method of characterizing block mask overlay tolerance of an integrated circuit design, said method comprising the steps of:
 obtaining a physical test integrated circuit having a plurality of repeating circuit portions corresponding to said integrated circuit design, a first of said portions being fabricated with a nominal block mask location, additional ones of said portions being deliberately fabricated with predetermined progressive increased offset of said block mask location from said nominal block mask location;   for each of said portions, determining a difference in threshold voltage between a first field effect transistor and a second field effect transistor, wherein said predetermined progressive increased offset of said block mask location is in a direction from said first field effect transistor to said second field effect transistor; and   determining said block mask overlay tolerance at a value of said progressive increased offset corresponding to an inflection of said difference in threshold voltage from a zero difference;   wherein said obtaining step comprises fabricating said physical test integrated circuit;   wherein said integrated circuit design comprises a static random access memory and wherein said fabricating comprises fabricating said repeating circuit portions as test static random access memory cells; and   wherein in said step of determining said difference in threshold voltage between said first field effect transistor and said second field effect transistor, said first field effect transistor comprises one of a left-hand pull-up transistor and a right-hand pull-up transistor, and said second field effect transistor comprises another one of said left-hand pull-up transistor and said right-hand pull-up transistor.   
     
     
         2 . The method of  claim 1 , wherein:
 said fabricating said repeating circuit portions as test static random access memory cells comprises fabricating said test static random access memory cells as six-transistor cells modified such that:
 a left-hand pass gate transistor and a right-hand pass gate transistor are shorted; 
 a left-hand pull-down transistor and a right-hand pull-down transistor are shorted; and 
 an input voltage node is provided by electrically connecting gates of said left-hand pull-up transistor, said right-hand pull-up transistor, said left-hand pull-down transistor, and said right-hand pull-down transistor. 
   
     
     
         3 . A method of characterizing block mask overlay tolerance of an integrated circuit design, said method comprising the steps of:
 obtaining a physical test integrated circuit having a plurality of repeating circuit portions corresponding to said integrated circuit design, a first of said portions being fabricated with a nominal block mask location, additional ones of said portions being deliberately fabricated with predetermined progressive increased offset of said block mask location from said nominal block mask location;   for each of said portions, determining a difference in threshold voltage between a first field effect transistor and a second field effect transistor, wherein said predetermined progressive increased offset of said block mask location is in a direction from said first field effect transistor to said second field effect transistor; and   determining said block mask overlay tolerance at a value of said progressive increased offset corresponding to an inflection of said difference in threshold voltage from a zero difference;   wherein said obtaining step comprises fabricating said physical test integrated circuit;   wherein said integrated circuit design comprises a static random access memory and wherein said fabricating comprises fabricating said repeating circuit portions as test static random access memory cells; and   wherein in said step of determining said difference in threshold voltage between said first field effect transistor and said second field effect transistor, said first field effect transistor comprises one of a left-hand pass gate transistor and a right-hand pass gate transistor, and said second field effect transistor comprises another one of said left-hand pass gate transistor and said right-hand pass gate transistor.   
     
     
         4 . The method of  claim 3 , wherein:
 said fabricating said repeating circuit portions as test static random access memory cells comprises fabricating said test static random access memory cells as six-transistor cells modified such that:
 a left-hand pull-up transistor and a right-hand pull-up transistor are shorted; 
 a left-hand pull-down transistor and a right-hand pull-down transistor are shorted; 
 gates of said left-hand pull-up transistor, said right-hand pull-up transistor, said left-hand pull-down transistor, and said right-hand pull-down transistor are electrically interconnected; and 
 a word line is electrically interconnected with gates of said left-hand pass gate transistor and said right-hand pass gate transistor. 
   
     
     
         5 . A method of characterizing block mask overlay tolerance of an integrated circuit design, said method comprising the steps of:
 obtaining a physical test integrated circuit having a plurality of repeating circuit portions corresponding to said integrated circuit design, a first of said portions being fabricated with a nominal block mask location, additional ones of said portions being deliberately fabricated with predetermined progressive increased offset of said block mask location from said nominal block mask location;   for each of said portions, determining a difference in threshold voltage between a first field effect transistor and a second field effect transistor, wherein said predetermined progressive increased offset of said block mask location is in a direction from said first field effect transistor to said second field effect transistor;   determining said block mask overlay tolerance at a value of said progressive increased offset corresponding to an inflection of said difference in threshold voltage from a zero difference;   obtaining an actual integrated circuit conforming to said integrated circuit design, said actual integrated circuit having formed thereon on-chip monitoring circuitry configured to determine threshold voltage difference between at least two actual transistors on said actual integrated circuit;   measuring said threshold voltage difference between said at least two actual transistors on said actual integrated circuit; and   determining actual block mask overlay in said actual integrated circuit by correlating said measured threshold voltage difference to results of said step of, for each of said portions, determining said difference in threshold voltage between said first field effect transistor and said second field effect transistor.   
     
     
         6 . The method of  claim 5 , wherein said step of obtaining said actual integrated circuit comprises fabricating said actual integrated circuit. 
     
     
         7 . The method of  claim 6 , wherein:
 said fabricating comprises forming said on-chip monitoring circuitry as a plurality of repeating circuit structures, each of said repeating circuit structures in turn comprising:
 a left-hand p-type field effect transistor having a first drain-source terminal coupled to a supply voltage node, a gate, and a second drain source terminal coupled to said gate; 
 a right-hand p-type field effect transistor having a first drain-source terminal coupled to said supply voltage node, a gate coupled to said gate of said left-hand p-type field effect transistor, and a second drain source terminal; 
 a left-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said left-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to a selective ground; 
 a right-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said right-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to said selective ground; 
   said gates of said left-hand n-type field effect transistors and said right-hand n-type field effect transistors are interconnected with an input voltage terminal; and   said measuring comprises measuring an average output voltage at said second drain source terminal of said right-hand p-type field effect transistor.   
     
     
         8 . The method of  claim 6 , wherein:
 said fabricating comprises forming said on-chip monitoring circuitry as a plurality of repeating circuit structures, each of said repeating circuit structures in turn comprising:
 a left-hand p-type field effect transistor having a first drain-source terminal coupled to a supply voltage node, a gate, and a second drain source terminal coupled to said gate; 
 a right-hand p-type field effect transistor having a first drain-source terminal coupled to said supply voltage node, a gate coupled to said gate of said left-hand p-type field effect transistor, and a second drain source terminal; 
 a left-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said left-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to a selective ground; 
 a right-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said right-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to said selective ground; 
   said gates of said left-hand n-type field effect transistors are interconnected with a first input voltage terminal and said gates of said right-hand n-type field effect transistors are interconnected with a second input voltage terminal; and   said measuring comprises sweeping voltage at said first input voltage terminal with voltage at said second input voltage terminal fixed, until an average output voltage at said second drain source terminal of said right-hand p-type field effect transistor equals zero.   
     
     
         9 . A method comprising:
 obtaining an actual integrated circuit conforming to a proposed integrated circuit design, said actual integrated circuit having formed thereon on-chip monitoring circuitry configured to determine threshold voltage difference between at least two actual transistors on said actual integrated circuit;   measuring said threshold voltage difference between said at least two actual transistors on said actual integrated circuit; and   determining actual block mask overlay in said actual integrated circuit by correlating said measured threshold voltage difference to results of testing on said proposed integrated circuit design.   
     
     
         10 . The method of  claim 9 , wherein said step of obtaining said actual integrated circuit comprises fabricating said actual integrated circuit. 
     
     
         11 . The method of  claim 10 , wherein:
 said fabricating comprises forming said on-chip monitoring circuitry as a plurality of repeating circuit structures, each of said repeating circuit structures in turn comprising:
 a left-hand p-type field effect transistor having a first drain-source terminal coupled to a supply voltage node, a gate, and a second drain source terminal coupled to said gate; 
 a right-hand p-type field effect transistor having a first drain-source terminal coupled to said supply voltage node, a gate coupled to said gate of said left-hand p-type field effect transistor, and a second drain source terminal; 
 a left-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said left-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to a selective ground; 
 a right-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said right-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to said selective ground; 
   said gates of said left-hand n-type field effect transistors and said right-hand n-type field effect transistors are interconnected with an input voltage terminal; and   said measuring comprises measuring an average output voltage at said second drain source terminal of said right-hand p-type field effect transistor.   
     
     
         12 . The method of  claim 10 , wherein:
 said fabricating comprises forming said on-chip monitoring circuitry as a plurality of repeating circuit structures, each of said repeating circuit structures in turn comprising:
 a left-hand p-type field effect transistor having a first drain-source terminal coupled to a supply voltage node, a gate, and a second drain source terminal coupled to said gate; 
 a right-hand p-type field effect transistor having a first drain-source terminal coupled to said supply voltage node, a gate coupled to said gate of said left-hand p-type field effect transistor, and a second drain source terminal; 
 a left-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said left-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to a selective ground; 
 a right-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said right-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to said selective ground; 
   said gates of said left-hand n-type field effect transistors are interconnected with a first input voltage terminal and said gates of said right-hand n-type field effect transistors are interconnected with a second input voltage terminal; and   said measuring comprises sweeping voltage at said first input voltage terminal with voltage at said second input voltage terminal fixed, until an average output voltage at said second drain source terminal of said right-hand p-type field effect transistor equals zero.   
     
     
         13 . An on-chip monitoring circuit for determining threshold voltage difference, comprising:
 a supply voltage node;   a selective ground; and   a plurality of repeating circuit structures, each of said repeating circuit structures in turn comprising:
 a left-hand p-type field effect transistor having a first drain-source terminal coupled to said supply voltage node, a gate, and a second drain source terminal coupled to said gate; 
 a right-hand p-type field effect transistor having a first drain-source terminal coupled to said supply voltage node, a gate coupled to said gate of said left-hand p-type field effect transistor, and a second drain source terminal; 
 a left-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said left-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to said selective ground; and 
 a right-hand n-type field effect transistor having a first drain-source terminal coupled to said second drain source terminal of said right-hand p-type field effect transistor; a gate, and a second drain source terminal coupled to said selective ground. 
   
     
     
         14 . The circuit of  claim 13 , further comprising an input voltage terminal, wherein said gates of said left-hand n-type field effect transistors and said right-hand n-type field effect transistors are interconnected with said input voltage terminal, and wherein said second drain source terminal of said right-hand p-type field effect transistor comprises an average output voltage measurement node. 
     
     
         15 . The circuit of  claim 13 , further comprising a first input voltage terminal and a second input voltage terminal, wherein said gates of said left-hand n-type field effect transistors are interconnected with said first input voltage terminal and said gates of said right-hand n-type field effect transistors are interconnected with said second input voltage terminal, and wherein said second drain source terminal of said right-hand p-type field effect transistor comprises an average output voltage measurement node.