Nonvolatile memory device and method for fabricating the same

Abstract

A nonvolatile memory device includes gate structures formed over a substrate, each gate structure including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate that are sequentially stacked, a protective layer formed on sidewalls of the floating gate, and a second insulating layer covering the gate structures and having an air gap formed between the gate structures, wherein an adhesive strength between the second insulating layer and the protective layer is smaller than an adhesive strength between the second insulating layer and the gate structure.

1 - 9 . (canceled) 
     
     
         10 . A method for fabricating a nonvolatile memory device, comprising:
 sequentially forming a tunnel insulating layer, a first conductive layer for a floating gate, an inter-gate dielectric layer, and a second conductive layer for a control gate over a substrate;   forming gate structures over the substrate, each gate structure formed by etching the second conductive layer, the inter-gate dielectric layer, and the first conductive layer; and   forming a protective layer pattern on at least sidewalls of the etched first conductive layer, the protective layer pattern blocking impurities from being transferred from or to the floating gate.   
     
     
         11 . The method of  claim 10 , further comprising forming a first insulating layer on the surface of the etched second conductive layer, after the second conductive layer is etched. 
     
     
         12 . The method of  claim 11 , wherein an adhesive strength between the first insulating layer and the protective layer pattern is smaller than an adhesive strength between the protective layer pattern and the first conductive layer. 
     
     
         13 . The method of  claim 11 , wherein the twilling of the first insulating layer is performed by a dry-oxidation process or atomic layer deposition (ALD) process. 
     
     
         14 . The method of  claim 10 , wherein the forming of the protective layer pattern comprises:
 forming a protective layer on sidewalls of the etched first conductive layer and the tunnel insulating layer; and   removing the protective layer on the tunnel insulating layer through a dry-etch process.   
     
     
         15 . The method of  claim 10 , wherein the protective layer pattern is further formed on a part or all of the gate structure excluding the etched first conductive layer. 
     
     
         16 . The method of  claim 10 , wherein an adhesive strength between the tunnel insulating layer and the protective layer pattern is smaller than an adhesive strength between the protective layer pattern and the first conductive layer. 
     
     
         17 . The method of  claim 10 , wherein the protective layer pattern comprises Ge. 
     
     
         18 . The method of  claim 11 , further comprising removing the first insulating layer, after the forming of the protective layer pattern. 
     
     
         19 . The method of  claim 11 , wherein the first insulating layer or the tunnel insulating layer comprises oxide. 
     
     
         20 . The method of  claim 10 , further comprising forming a second insulating layer covering the gate structures and having an air gap formed between the gate structures, after the forming of the protective layer patterns. 
     
     
         21 . The method of  claim 20 , wherein an adhesive strength between the second insulating layer and the protective layer patterns is smaller than an adhesive strength between the second insulating layer and the second conductive layer or an adhesive strength between the second insulating layer and the inter-gate dielectric layer. 
     
     
         22 . The method of  claim 20 , wherein the second insulating layer comprises oxide.