Semiconductor integrated circuit apparatus

Abstract

When a bus stop request control unit issues a module-specific bus stop request signal, a bus stop control unit coupled to a bus slave determines a module that serves as a bus master of the bus slave and on which the bus slave is dependent, for example, on the basis of information in a dependence setting register. The bus stop control unit then outputs a prior bus stop request signal to the module on which the bus slave is dependent, so as to stop use of a bus of the module. Upon receipt of a module-specific bus stop completion signal indicating that processing of stop of the bus of the module on which the bus slave is dependent is complete, the bus stop control unit outputs a module-specific bus stop request signal to the module which serves as a bus slave and whose bus is to be stopped.

What is claimed is: 
     
         1 . A semiconductor integrated circuit apparatus comprising:
 a plurality of modules; and   a plurality of bus stop control units provided corresponding to the plurality of modules, respectively, each configured to request stop of a bus to the corresponding module, the plurality of bus stop control unit including,   a first bus stop control unit, which is provided for a first module of the plurality of modules, identifying a second module of the plurality of modules upon based on a first bus stop request signal, outputting a second bus stop request signal and requesting to the first module a bus stop on reception of a bus stop completion from the second module, the second module being a bus master to the first module,   a second bus stop control unit, which is provided for the second module, receiving the second bus stop request signal from the first bus stop control unit, identifying a third module of the plurality of modules upon based on the second bus stop request signal, outputting a third bus stop request signal, requesting to the second module a bus stop on reception of a bus stop completion from the third module, the third module being a bus master to the second module, and   a third bus stop control unit, which is provided for the third module, requesting to the third module a bus stop after receiving the third bus stop request signal from the second bus stop control unit.   
     
     
         2 . The semiconductor integrated circuit apparatus according to  claim 1 , further comprising
 a storage unit storing first information for identifying that the second module is a bus master to the first module and second information for identifying that the third module is a bus master to the second module,   wherein the first and second bus stop control units refer to the first and second information, respectively, to provide the second and third bus stop request signal.   
     
     
         3 . The semiconductor integrated circuit apparatus according to  claim 1 , further comprising:
 a power control unit that performs power control on at least the first module; and   a bus stop request control unit that outputs the first bus stop request signals to the first bus stop control unit in accordance with a power control signal outputted by the power control unit and, when stop of a bus of the first module is completed, outputs a bus stop completion signal to the power control unit,   wherein upon receipt of the bus stop completion signal from the bus stop request control unit, the power control unit performs power saving control on the first module.