Solid-state imaging device and camera system

Abstract

A solid-state imaging device and a camera system are provided. The solid-state imaging device capable of performing an intermittent operation includes a pixel unit and a pixel signal readout unit for reading out a pixel signal from the pixel unit in units of a plurality of pixels for each column. The pixel signal readout circuit includes a plurality of comparators and a plurality of counters whose operations are controlled by outputs of the comparators. Each of the comparators includes an initializing switch for determining an operating point for each column at a start of row operation, and is configured so that an initialization signal to be applied to the initializing switch is controlled independently in parallel only a basic unit of the initialization signal used for a horizontal intermittent operation, and the initializing switch is held in an off-state at a start of non-operating row.

1 . An imaging device comprising:
 a first analog-to-digital converter including:
 a first comparator circuit configured to output a first determination signal based on a first analog signal; 
 a first storing circuit configured to store a first digital signal based on the first determination signal; and 
 a first reset switch configured to reset the first comparator at least before an analog-to-digital conversion operation; and 
   a second analog-to-digital converter including:
 a second comparator circuit configured to output a second determination signal based on a second analog signal; 
 a second storing circuit configured to store a second digital signal based on the second determination signal; 
 a second reset switch configured to reset the second comparator at least before the analog-to-digital conversion operation; wherein 
   while the first analog-to-digital converter is in an ON-state, the second analog-to-digital converter is configured to be selectively switched between an OFF-state and an ON-state.   
     
     
         2 . The imaging device according to  claim 1 , further comprising:
 a pixel unit including a plurality of pixels arranged in a matrix, respective ones of the plurality of pixels having a photoelectric conversion device, a transfer transistor, a reset transistor, and an amplifier transistor.   
     
     
         3 . The imaging device according to  claim 1 , further comprising a counter. 
     
     
         4 . The imaging device according to  claim 1 , further comprising first and a second counters, each of the first and second counters configured to receive an output signal from the first and second analog-to-digital converters, respectively. 
     
     
         5 . The imaging device according to  claim 4 , wherein the first and second counters are respectively connected to the first and second storing circuits. 
     
     
         6 . The imaging device according to  claim 1 , wherein the first and second analog-to-digital converters respectively include first and second gain amplifiers. 
     
     
         7 . An imaging device comprising:
 a first comparator configured to output a first determination signal based on a first analog signal, the first comparator including:
 a first pair of differential transistors and 
 a first transistor connected between a predetermined potential and the first pair of differential transistors, 
   a second comparator configured to output a second determination signal based on a second analog signal, the second comparator including:
 a second pair of differential transistors; and 
 a second transistor connected between the predetermined potential and the second pair of differential transistors, 
   wherein a gate of the first transistor is connected to a first control line, and a gate of the second transistor is connected to a second control line which is different from the first control line.   
     
     
         8 . The imaging device according to  claim 7 , wherein the first transistor is connected between the predetermined potential and a drain or a source of the first pair of differential transistors. 
     
     
         9 . The imaging device according to  claim 8 , wherein the second transistor is connected between the predetermined potential and a drain or a source of the second pair of differential transistors. 
     
     
         10 . The imaging device according to  claim 8 , wherein the source of the first pair of differential transistors is connected to the drain of the first transistor. 
     
     
         11 . The imaging device according to  claim 8 , wherein the source of the second pair of differential transistors is connected to the drain of the first transistor. 
     
     
         12 . The imaging device according to  claim 8 , wherein the drain of the first pair of differential transistors is connected to the source of the first transistor. 
     
     
         13 . The imaging device according to  claim 12 , wherein the drain of the second pair of differential transistors is connected to the source of the second transistor 
     
     
         14 . The imaging device according to  claim 7 , wherein the first comparator includes a first reset switch connected between a gate of one of the first pair of differential transistors and a source or a drain of the one of the first pair of differential transistors. 
     
     
         15 . The imaging device according to  claim 7 , wherein the second comparator includes a second reset switch connected between a control terminal of one of the second pair of differential transistors and a source or a drain of the one of the second pair of differential transistors. 
     
     
         16 . The imaging device according to  claim 7 , further comprising:
 a pixel unit including a plurality of pixels arranged in a matrix, respective ones of the plurality of pixels having a photoelectric conversion device, a transfer transistor, a reset transistor, and an amplifier transistor.   
     
     
         17 . The imaging device according to  claim 7 , further comprising a counter. 
     
     
         18 . The imaging device according to  claim 7 , further comprising a first counter and a second counter. 
     
     
         19 . The imaging device according to  claim 18 , wherein the first counter and the second counter are respectively connected to the first comparator and the second comparator. 
     
     
         20 . The imaging device according to  claim 17 , further comprising a storing circuit. 
     
     
         21 . The imaging device according to  claim 18 , further comprising a first storing circuit and a second storing circuit. 
     
     
         22 . The imaging device according to  claim 21 , wherein the first storing circuit and the second storing circuit are respectively connected to the first counter and the second counter. 
     
     
         23 . An electronic apparatus comprising an imaging device, the imaging device comprising:
 a first analog-to-digital converter including:
 a first comparator circuit configured to output a first determination signal based on a first analog signal; 
 a first storing circuit configured to store a first digital signal based on the first determination signal; and 
 a first reset switch configured to reset the first comparator at least before an analog-to-digital conversion operation; and 
   a second analog-to-digital converter including:
 a second comparator circuit configured to output a second determination signal based on a second analog signal; 
 a second storing circuit configured to store a second digital signal based on the second determination signal; 
 a second reset switch configured to reset the second comparator at least before the analog-to-digital conversion operation; wherein, 
   while the first analog-to-digital converter is in an ON-state, the second analog-to-digital converter is configured to be selectively switched between an OFF-state and an ON-state.   
     
     
         24 . An electronic apparatus comprising an imaging device, the imaging device comprising,
 a first comparator configured to output a first determination signal based on a first analog signal, the first comparator including:
 a first pair of differential transistors, and 
 a first transistor connected between a predetermined potential and the first pair of differential transistors, 
   a second comparator configured to output a second determination signal based on a second analog signal, the second comparator including:
 a second pair of differential transistors; and 
 a second transistor connected between the predetermined potential and the second pair of differential transistors, 
   wherein a control terminal of the first transistor is connected to a first control line, and a control terminal of the second transistor is connected to a second control line which is different from the first control line.   
     
     
         25 . The electronic apparatus according to  claim 24 , wherein the first transistor is connected between the predetermined potential and a drain or a source of the first pair of differential transistors. 
     
     
         26 . The electronic apparatus according to  claim 25 , wherein the second transistor is connected between the predetermined potential and a drain or a source of the second pair of differential transistors. 
     
     
         27 . The electronic apparatus according to  claim 24 , wherein the first comparator includes a first reset switch connected between a gate of one of the first pair of differential transistors and a source or a drain of the one of the first pair of differential transistors. 
     
     
         28 . The electronic apparatus according to  claim 24 , wherein the second comparator includes a second reset switch connected between a control terminal of one of the second pair of differential transistors and a source or a drain of the one of the second pair of differential transistors. 
     
     
         29 . The electronic apparatus according to  claim 24 , further comprising:
 a pixel unit including a plurality of pixels arranged in a matrix, respective ones of the plurality of pixels having a photoelectric conversion device, a transfer transistor, a reset transistor, and an amplifier transistor.   
     
     
         30 . The electronic apparatus according to  claim 24 , further comprising a counter.