IQ Gain Imbalance Correction For Receivers Employing Sigma-Delta Analog To Digital Conversion

Abstract

An apparatus for improving a gain imbalance between an in-phase and quadrature component recovered by a receiver is provided. The apparatus includes a first transition counter configured to count a number of bit transitions in a first sequence of one-bit values provided by a first sigma-delta modulator based on the in-phase component, and a second transition counter configured to count a number of bit transitions in a second sequence of one-bit values provided by a second sigma-delta modulator based on the quadrature component. The apparatus further includes a gain monitor configured to: (1) determine a first and second power level, proportional to a power of the in-phase and quadrature components respectively, using the number of bit transitions in the first and second sequences, and (2) adjust a gain of one of the in-phase and quadrature components based on a ratio between the first and second power levels.

What is claimed is: 
     
         1 . A receiver comprising:
 a first sigma-delta modulator configured to convert an in-phase component of a received signal into a first discrete time signal comprising a first sequence of one-bit values;   a second sigma-delta modulator configured to convert a quadrature component of the received signal into a second discrete time signal comprising, a second sequence of one-bit values; and   a gain monitor configured to adjust a gain of the receiver based on a ratio between a first power level, determined based on a number of bit transitions in the first sequence of one-bit values, and a second power level, determined based on a number of bit transitions in the second sequence of one-bit values.   
     
     
         2 . The receiver of  claim 1 , wherein the gain monitor comprises:
 a first adder configured to add a first constant value to the number of bit transitions in the first sequence to determine the first power level; and   a second adder configured to add a second constant value to the number of bit transitions in the second sequence to determine the second power level.   
     
     
         3 . The receiver of  claim 2 , wherein the gain monitor further comprises:
 a divider configured to divide the first power level by the second power level to determine the ratio.   
     
     
         4 . The receiver of  claim 3 , wherein the gain is associated with the in-phase component. 
     
     
         5 . The receiver of  claim 2 , wherein the gain monitor further comprises:
 a divider configured to divide the second power level by the first power level to determine the ratio.   
     
     
         6 . The receiver of  claim 3 , wherein the gain is associated with the quadrature component. 
     
     
         7 . The receiver of  claim 1 , further comprising:
 a comparator configured to compare a first one-bit value of the first sequence to a second one-bit value of the first sequence to determine if the first one-bit value is equal to the second one-hit value, wherein first one-bit value and second one-bit value are immediately adjacent to each other in the first sequence; and   an accumulator configured to increment the number of bit transitions in the first sequence of one-bit values if the first one-bit value is not equal to the second one-bit value as determined by the comparator.   
     
     
         8 . The receiver of  claim 7 , further comprising:
 a memory element configured to store the first one-bit value of the first sequence.   
     
     
         9 . A method for calibrating a receiver, the method comprising:
 converting an in-phase component of a received signal into a first discrete time signal comprising a first sequence of one-bit values;   converting a quadrature component of the received signal into a second discrete time signal comprising a second sequence of one-bit values; and   adjusting a gain of the receiver based on a ratio between a first power level, determined based on a number of bit transitions in the first sequence of one-bit values, and a second power level, determined based on a number of bit transitions in the second sequence of one-bit values.   
     
     
         10 . The method of  claim 9 , further comprising:
 adding a first constant value to the number of bit transitions in the first sequence to determine the first power level; and   adding a second constant value to the number of bit transitions in the second sequence to determine the second power level.   
     
     
         11 . The method of  claim 9 , wherein the adjusting the gain further comprises:
 dividing the first power level by the second power level to determine the ratio.   
     
     
         12 . The method of  claim 11 , wherein the gain is associated with the in-phase component. 
     
     
         13 . The method of  claim 9 , wherein the adjusting the gain further comprises:
 dividing the second power level by the first power level to determine the ratio.   
     
     
         14 . The method of  claim 13 , wherein the gain is associated with the quadrature component. 
     
     
         15 . The method of  claim 9 , further comprising:
 comparing a first one-bit value of the first sequence to a second one-bit value of the first sequence to determine if the first one-bit value is equal to the second one-bit value, wherein first one-bit value and second one-bit value are immediately adjacent to each other in the first sequence; and   incrementing the number of bit transitions in the first sequence of one-bit values if the first one-bit value is not equal to the second one-bit value.   
     
     
         16 . A method for calibrating a receiver, the method comprising:
 determining a first power level using a number of bit transitions in a first sequence of one-bit values, wherein the first sequence of one-bit values is provided by a first sigma-delta modulator based on an in-phase component of a received signal;   determining a second power level using a number of bit transitions in a second sequence of one-bit values, where the second sequence of one-bit values is provided by a second sigma-delta modulator based on a quadrature component of the received signal; and   adjusting a gain of the receiver based on a ratio between the first power level and the second power level.   
     
     
         17 . The method of  claim 16 , further comprising:
 adding a first constant value to the number of bit transitions in the first sequence to determine the first power level, and   adding a second constant value to the number of bit transitions in the second sequence to determine the second power level.   
     
     
         18 . A method comprising:
 using a sigma-delta modulator to convert an analog signal into a discrete time signal comprising a sequence of one-bit values;   counting a number of bit transitions in the sequence of one-bit values; and   determining a power level of the analog signal using the number of bit transitions in the sequence.   
     
     
         19 . The method of  claim 18 , wherein determining the power level using the number of bit transitions in the first sequence comprises:
 normalizing the number of bit transitions in the sequence of one-bit values by a total number of bits in the sequence.   
     
     
         20 . The method of  claim 19 , further comprising:
 comparing the power level to a threshold; and   adjusting a gain of the sigma-delta modulator based on the comparison.