US2015171165A1PendingUtilityA1
Bonded strained semiconductor with a desired surface orientation and conductance direction
Est. expiryAug 3, 2026(expired)· nominal 20-yr term from priority
Inventors:Leonard Forbes
H10D 84/0167H10D 84/038H10D 62/405H10D 62/292H10D 30/798H10D 30/792H10D 30/0278H10D 30/751H01L 29/045H01L 29/1054H01L 29/7849
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Claims
Abstract
According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A structure, comprising:
a substrate; a crystalline semiconductor layer bonded to the substrate, the semiconductor layer having a surface orientation and a desired channel conductance direction for the surface orientation, the crystalline semiconductor layer having a local strained region; and a gate oxide over the local strained region, a gate over the gate oxide, and first and second source/drain regions to provide a channel region with the desired channel conductance direction within in the local strained region.
2 . The structure of claim 1 , wherein the local strained region includes a uniaxial tensile strain.
3 . The structure of claim 1 , wherein the local strained region includes a uniaxial compressive strain.
4 . The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (100) crystalline orientation and the desired channel conductance direction is a <110> direction with respect to the crystalline orientation.
5 . The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (110) crystalline orientation and the desired channel conductance direction is a <100> direction with respect to the crystalline orientation.
6 . The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (111) crystalline orientation and the desired channel conductance direction is a <110> direction with respect to the crystalline orientation.
7 . The structure of claim 1 , wherein the crystalline semiconductor layer includes a silicon layer with a (100) crystalline orientation and the desired channel conductance direction is a <100> direction with respect to the crystalline orientation.
8 . The structure of claim 1 , wherein the local strained region has a strain greater than 0.75%.
9 . The structure of claim 1 , wherein the local strained region has a strain within a range between approximately 0.75% and approximately 1.5%.
10 . The structure of claim 1 , wherein the local strained region has a strain within a range between approximately 1.0% and approximately 1.2%.
11 . The structure of claim 1 , wherein the crystalline semiconductor layer has a thickness of approximately 1000 Å or less.
12 . The structure of claim 1 , wherein the crystalline semiconductor layer has a thickness of approximately 300 Å to 1000 Å.
13 . A structure, comprising:
a substrate; a crystalline silicon layer bonded to the substrate, the semiconductor layer having a thickness of approximately 1000 Å or less and having a surface orientation and a desired channel conductance direction for the surface orientation, the crystalline semiconductor layer having a local strained region that includes a uniaxial strain; and a gate oxide over the local strained region, a gate over the gate oxide, and first and second source/drain regions to provide a channel region with the desired channel conductance direction within in the local strained region.
14 . The structure of claim 13 , wherein the uniaxial strain is compressive.
15 . The structure of claim 13 , wherein the uniaxial strain is tensile.
16 . The structure of claim 13 , wherein the local strained region has a strain within a range between approximately 0.75% and approximately 1.5%.
17 . The structure of claim 13 , wherein the local strain region includes a first local strain region that includes a tensile strain, the structure further including a second local strain region that includes a compressive strain.
18 . A structure, comprising:
a substrate; a first crystalline silicon layer bonded to the substrate, the first layer having a first surface orientation and a first desired channel conductance direction for the first surface orientation, the first layer having a first local strained region; a first device formed using the first layer, including a first gate oxide over the first local strained region, a first gate over the first gate oxide, and first and second source/drain regions to provide a first channel region with the first desired channel conductance direction within in the first local strained region; a second crystalline silicon layer bonded to the substrate, the second layer having a second surface orientation and a second desired channel conductance direction for the second surface orientation, the second layer having a second local strained region; and a second device formed using the second layer, including a second gate oxide over the second local strained region, a second gate over the second gate oxide, and third and fourth source/drain regions to provide a second channel region with the second desired channel conductance direction within in the second local strained region.
19 . The structure of claim 18 , wherein the first layer is a (100) silicon layer, the first desired channel conductance is in the <110> direction with respect to the (100) silicon layer, the second layer is (110) silicon layer, and the second desired channel conductance is in the <100> direction with respect to the (110) silicon layer.
20 . The structure of claim 18 , wherein the first local strained region includes a tensile strain and the second local strained region includes a compressive strain.Join the waitlist — get patent alerts
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