Methods for device fabrication using pitch reduction and related devices

Abstract

Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

1 . A method for semiconductor device fabrication, comprising:
 photolithographically forming a first pattern of features over a substrate, the features of the first pattern of features having a first width;   forming a second pattern of pitch-multiplied spacers having a second width less than the first width subsequent to photolithographically forming the first pattern of features; and   consolidating the first pattern of features and the second pattern of pitch-multiplied spacers into a modified pattern of spacers and features.   
     
     
         2 . The method of  claim 1 , wherein consolidating the first pattern of features and the second pattern of pitch-multiplied spacers into a modified pattern of spacers and features comprises forming a protective mask over the first pattern of features and the second pattern of pitch-multiplied spacers to selectively expose portions of the first pattern of features and the second pattern of pitch-multiplied spacers, etching the selectively exposed portions of the first pattern of features and the second pattern of pitch-multiplied spacers to remove the exposed portions of the first pattern of features and the second pattern of pitch-multiplied spacers. 
     
     
         3 . The method of  claim 2 , further comprising stripping the protective mask from the modified pattern of spacers and features, and thereafter transferring the modified pattern of spacers and features into the substrate. 
     
     
         4 . A semiconductor device structure, comprising:
 a semiconductor substrate;   a pattern of features at a photolithographic resolution over the substrate in a first region, the features having a first width;   a pattern of sub-photolithographic resolution spacers over the substrate in a second region, the pattern of sub-photolithographic resolution spacers comprising a plurality of spacers laterally adjacent and on opposite sides of a photoresist; the sub-lithographic spacers having a second width less than the first width.   
     
     
         5 . The semiconductor device structure of  claim 4 , wherein the second region is a central array region and the first region is a peripheral region. 
     
     
         6 . The semiconductor device structure of  claim 4 , wherein the pattern of sub-photolithographic resolution spacers is configured as an array. 
     
     
         7 . The semiconductor device structure of  claim 4 , further comprising a protective material around and over at least a portion of the pattern of features at a photolithographic resolution and the pattern of sub-photolithographic resolution spacers. 
     
     
         8 . The semiconductor device structure of  claim 7 , wherein the pattern of sub-photolithographic resolution spacers comprises a spacer having at least two separate portions not covered by the protective material. 
     
     
         9 . The semiconductor device structure of  claim 4 , wherein the sub-photolithographic resolution spacers comprise a material selected from the group consisting of silicon, silicon oxides, and silicon nitrides. 
     
     
         10 . The method of  claim 1 , further comprising forming a mask over the substrate before photolithographically forming the first pattern of features. 
     
     
         11 . The method of  claim 10 , wherein forming the mask comprises depositing amorphous carbon, amorphous silicon, a silane oxide, a nitride, or Al 2 O 3 . 
     
     
         12 . The method of  claim 1 , wherein photolithographically forming a first pattern of features over a substrate comprises exposing a photoresist overlying a hard mask to radiation through a reticle. 
     
     
         13 . The method of  claim 12 , wherein photolithographically forming a first pattern of features over a substrate further comprises anisotropically etching the hard mask. 
     
     
         14 . The method of  claim 1 , wherein forming a second pattern of pitch-multiplied spacers comprises forming a photoresist material over the first pattern of features. 
     
     
         15 . The method of  claim 14 , further comprising exposing the photoresist material to radiation through a reticle to form lines of the photoresist material separated by trenches. 
     
     
         16 . The method of  claim 15 , further comprising etching the photoresist material to increase a width of the trenches and decrease a width of the lines of the photoresist material. 
     
     
         17 . The method of  claim 16 , further comprising conformally depositing a spacer material over the first pattern of features and the second pattern of pitch-multiplied spacers. 
     
     
         18 . The method of  claim 17 , further comprising anisotropically etching the spacer material to form spacers of the second pattern of pitch-multiplied spacers. 
     
     
         19 . The method of  claim 18 , further comprising removing at least a portion of the photoresist material between adjacent spacers of the second pattern of pitch-multiplied spacers. 
     
     
         20 . A method for semiconductor device fabrication, comprising:
 forming a hard mask over a substrate;   photolithographically forming a first pattern of features over the hard mask, the features of the first pattern of features having a first width;   forming a second pattern of pitch-multiplied spacers having a second width less than the first width over the hard mask after photolithographically forming the first pattern of features; and   removing a portion of the hard mask to transfer the first pattern of features and the second pattern of pitch-multiplied spacers into a modified pattern of spacers and features in the hard mask.