Semiconductor device and data processing system

Abstract

A semiconductor device having a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell, so that the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced.

What is claimed: 
     
         1 . A semiconductor device comprising:
 a memory cell including a capacitor storing data as charge and a select transistor having a floating body in an electrically floating state formed between a source region and a drain region, the capacitor and the select transistor are connected in series;   a bit line connected to the select transistor;   a bit line control circuit setting the bit line to a first potential during a non-access period of the memory cell in a data retention state and setting the bit line being set to the first potential to a second potential different from the first potential during an access period of the memory cell in a non-conductive state of the select transistor; and   a sense amplifier amplifying a signal read out from the memory cell through the bit line being set to the second potential when the select transistor is controlled to be conductive.