Cmos devices with stressed channel regions, and methods for fabricating the same

Abstract

Complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions are provided. Each CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a field effect transistor (FET) having a channel region located in a semiconductor device structure, said semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes; and   one or more stressor layers located over said one or more additional surfaces of the semiconductor device structure and are arranged and constructed to apply stress to the channel region of the FET, said one or more stressor layers have a lattice constant larger than that of the semiconductor device structure, so that compressive stress is created in the stressor layers, wherein the one or more additional surfaces form obtuse angles with the top surface of the semiconductor device structure, and said one or more stressor layers apply compressive stress to the channel region of the FET.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the semiconductor device structure comprises single crystal silicon. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the first and second sets of equivalent crystal planes are selected from the group consisting of the {100}, {110}, and {111} planes of silicon. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the semiconductor device structure is located over a substrate. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the substrate comprises at least one insulator layer with a base semiconductor substrate layer thereunder. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the semiconductor device structure is located in a bulk semiconductor substrate structure. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the one or more stressor layers comprise a silicon germanium alloy. 
     
     
         8 . A semiconductor device comprising:
 an n-channel field effect transistor (n-FET) having an n-doped channel region located in a semiconductor device structure, said semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes; and   one or more stressor layers located over said one or more additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile stress to the n-doped channel region of the FET, wherein the one or more stressor layers have a lattice constant smaller than that of the semiconductor device structure, so that tensile stress is created in the stressor layers.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the one or more additional surfaces form obtuse angles with the top surface of the semiconductor device structure, and said one or more stressor layer with intrinsic tensile stress are located over said one or more additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile stress to the n-doped channel region of the n-FET. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the semiconductor device structure comprises single crystal silicon. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the first and second sets of equivalent crystal planes are selected from the group consisting of the {100}, {110}, and {111} planes of silicon. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the semiconductor device structure is located over a substrate. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the substrate comprises at least one insulator layer with a base semiconductor substrate layer thereunder. 
     
     
         14 . The semiconductor device of  claim 8 , wherein the one or more stressor layers carbon-doped silicon. 
     
     
         15 . A method for forming a semiconductor device, comprising:
 forming a semiconductor device structure having a top surface that is oriented along one of a first set of equivalent crystal planes and one or more additional surfaces that are oriented along a second, different set of equivalent crystal planes;   forming one or more stressor layers over said one or more additional surfaces of the semiconductor device structure, wherein said one or more stressor layers are arranged and constructed to apply stress to the semiconductor device structure; and   forming a field effect transistor (FET) with a channel region located in the semiconductor device structure.   
     
     
         16 . The method of  claim 15 , wherein the semiconductor device structure is formed by:
 forming a semiconductor device layer having at least a top surface oriented along one of a first set of equivalent crystallographic planes;   selectively covering a portion of the semiconductor device layer;   anisotropically etching an uncovered portion of the semiconductor device layer to expose at least one of a bottom surface and one or more sidewall surfaces of the semiconductor device layer, said bottom surface and said sidewall surfaces are oriented along the first set of equivalent crystallographic planes; and   crystallographically etching the at least one of the bottom surface and sidewall surfaces of the semiconductor device layer to form one or more additional surfaces that are oriented along a second, different set of equivalent crystallographic planes.   
     
     
         17 . The method of  claim 15 , wherein the one or more stressor layers have a lattice constant larger than that of the semiconductor device structure, so that compressive stress is created in the stressor layers, and the one or more additional surfaces form acute angles with the top surface of the semiconductor device structure, and said one or more stressor layers apply tensile stress to the channel region of the FET. 
     
     
         18 . The method of  claim 15 , wherein the one or more stressor layers have a lattice constant larger than that of the semiconductor device structure, so that compressive stress is created in the stressor layers, and the one or more additional surfaces form obtuse angles with the top surface of the semiconductor device structure, and said one or more stressor layers apply compressive stress to the channel region of the FET. 
     
     
         19 . The method of  claim 15 , wherein the one or more stressor layers have a lattice constant smaller than that of the semiconductor device structure, so that tensile stress is created in the stressor layers, and the one or more additional surfaces form acute angles with the top surface of the semiconductor device structure, and said one or more stressor layer apply compressive stress to the channel region of the FET. 
     
     
         20 . The method of  claim 15 , wherein the one or more stressor layers have a lattice constant smaller than that of the semiconductor device structure, so that tensile stress is created in the stressor layers, and the one or more additional surfaces form obtuse angles with the top surface of the semiconductor device structure, and said one or more stressor layer apply tensile stress to the channel region of the FET.