Semiconductor device and method of manufacturing the same

Abstract

A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

1 . A semiconductor device comprising:
 a substrate having a {111} plane of a silicon crystal structure and a top surface, wherein the {111} plane meets the top surface to form an interconnection line on the top surface;   a first stacked structure and a second stacked structure formed on the substrate, wherein each of the first and the second stacked structures includes a plurality of gate electrodes stacked on the semiconductor substrate; and   a transistor disposed between the first stacked structure and the second stacked structure on the substrate,   wherein the transistor includes a gate electrode extending in a first direction, a source region and a drain region,   wherein the source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction, and   wherein the interconnection line is extended at an angle with respect to the second direction.   
     
     
         2 . The device of  claim 1 , wherein the angle is greater than about 0 degree and is less than or equal to about 45 degree. 
     
     
         3 . The device of  claim 1 , wherein the plurality of gate electrodes are extended in a third direction crossing the interconnection line at about 45 degree. 
     
     
         4 . The device of  claim 1 , wherein the plurality of gate electrodes are extended in a third direction crossing the first direction and the second direction. 
     
     
         5 . The device of  claim 1 , wherein the first stacked structure includes an stepped end where each of the plurality of gate electrodes includes an exposed region where a contact hole is disposed on the exposed region, and
 wherein the stepped end of the first stacked structure is adjacent to the transistor.   
     
     
         6 . The device of  claim 1 , further comprising a vertical structure penetrating the plurality of gate electrodes. 
     
     
         7 . The device of  claim 6 , wherein each of the first and second stacked structures further comprises a plurality of insulating layers, wherein each of the plurality of insulating layers is interposed between two adjacent gate electrodes of the plurality of the gate electrodes. 
     
     
         8 . The device of  claim 7 , further comprising a plurality of horizontal structures, wherein each of the plurality of horizontal structures is disposed between each of the plurality of gate electrodes and each of the plurality of insulating layers and between the plurality of gate electrodes and the vertical structure. 
     
     
         9 . The device of  claim 6 , wherein the plurality of gate electrodes comprises a metallic material. 
     
     
         10 . The device of  claim 1 , wherein if top surface of the substrate has a {100} plane, a direction of the interconnection line is <110>. 
     
     
         11 . A method of manufacturing a semiconductor device, the method comprising:
 forming a device isolation layer defining a peripheral active pattern in a substrate;   forming a peripheral gate electrode crossing the peripheral active pattern in a first direction;   forming source and drain regions in the peripheral active pattern at both sides of the peripheral gate electrode, wherein the source and drain regions are arranged in a second direction crossing the first direction; and   forming a stacked structure on a top surface of the substrate, wherein the stacked structure includes a plurality of gate electrodes vertically stacked on the top surface of the substrate,   wherein an intersection line is extended at an angle with respect to the second direction, wherein the intersection line is a line where a {111} plane of the silicon crystal structure and the top surface of the substrate meet.   
     
     
         12 . The method of  claim 11 , wherein an orientation of the intersection line is <110> if the top surface of the substrate has a {100} plane. 
     
     
         13 . The method of  claim 11 , wherein the angle is greater than about 0° and is smaller than or equal to about 45°. 
     
     
         14 . The method of  claim 11 , wherein the substrate is a wafer having a flat zone of a {100} plane, and wherein the second direction is substantially parallel to a <100> direction. 
     
     
         15 . The method of  claim 11 , wherein the substrate is a wafer having a flat zone of a {110} plane, and wherein the second direction is substantially parallel to a <100> direction. 
     
     
         16 . The method of  claim 11 , wherein the plurality of gate electrodes are extended in a third direction crossing the interconnection line at about 45 degree. 
     
     
         17 . The method of  claim 11 , wherein the plurality of gate electrodes are extended in a third direction crossing the first direction and the second direction. 
     
     
         18 . A semiconductor device comprising:
 a peripheral circuit structure disposed on a first substrate having a silicon crystal structure, wherein a {111} plane of the first substrate meets a top surface of the first substrate to form an interconnection line on the top surface;   a cell array structure disposed on the peripheral circuit structure; and   a second substrate interposed between the peripheral circuit structure and the cell array structure,   wherein the cell array structure includes a plurality of gate electrode stacked on the second substrate,   wherein the peripheral circuit structure comprises a transistor having a gate electrode, a source region and a drain region, wherein the gate electrode is extended in a first direction and the source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction,   wherein the intersection line is extended at an angle with respect to the second direction.   
     
     
         19 . The device of  claim 18 , wherein the angle is greater than about 0 degree and is less than or equal to about 45 degree. 
     
     
         20 . The device of  claim 18 , wherein if top surface of the substrate has a {100} plane, a direction of the interconnection line is <110>.