Advanced interconnect with air gap

Abstract

Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

1 . An interconnect structure on a semiconductor substrate, the interconnect structure comprising:
 a dielectric layer;   an insulating material above the dielectric layer;   an array of metal lines formed in the insulating material; and   a plurality of air gaps positioned among the metal lines of the array, the air gaps being sealed by a capping film.   
     
     
         2 . The interconnect structure of  claim 1  wherein the semiconductor substrate contains electronic devices. 
     
     
         3 . The interconnect structure of  claim 1  wherein the dielectric layer is an ultra-low-k dielectric layer having a dielectric constant less than 2.0. 
     
     
         4 . The interconnect structure of  claim 1  wherein the insulator is a high modulus insulator having a dielectric constant in the range of about 3.5-4.5. 
     
     
         5 . The interconnect structure of  claim 4  wherein an effective dielectric constant of the high modulus insulator integrated with the capping film sealing the plurality of air gaps is less than about 2.0. 
     
     
         6 . The interconnect structure of  claim 4  wherein the high modulus insulator includes one or more of SiN, SiC, or SiC x N y . 
     
     
         7 . The interconnect structure of  claim 4  further comprising an encapsulation layer surrounding the metal lines. 
     
     
         8 . The interconnect structure of  claim 1  wherein the air gaps are tapered such that the top of each air gap is narrower than the bottom of the air gap. 
     
     
         9 . The interconnect structure of  claim 1  wherein the capping film is used as the encapsulating layer. 
     
     
         10 . The interconnect structure of  claim 1  wherein the metal lines are formed having a width-to-spacing ratio of 0.618. 
     
     
         11 . The interconnect structure of  claim 1 , further comprising a base layer below the dielectric layer, the base layer made of SiC x N y . 
     
     
         12 . The interconnect structure of  claim 1  wherein the capping film is a high aspect ratio film that includes SiC. 
     
     
         13 . A damascene interconnect structure comprising: an array of insulating columns among metal lines, each of the insulating columns having a tapered air gap extending vertically therein. 
     
     
         14 . The interconnect structure of  claim 13  wherein the insulating columns contain a high modulus material. 
     
     
         15 . The interconnect structure of  claim 13  wherein the insulating columns have an insulating column width and the metal lines have a metal line width, the metal line width being a certain percentage of the insulating column width, according to a golden ratio. 
     
     
         16 . A method comprising:
 forming a dielectric layer on a semiconductor substrate;   forming a high modulus insulator film on the dielectric layer;   patterning the high modulus insulator film using a hard mask to form trenches and vias among insulating columns;   conformally depositing a layer that forms air gaps within the insulating columns and encapsulates the trenches and vias; and   filling the encapsulated trenches and vias with metal.   
     
     
         17 . The method of  claim 16  wherein patterning the high modulus insulator film using the hard mask forms an array of insulating columns that are freestanding. 
     
     
         18 . The method of  claim 16  wherein the air gaps are tapered and extend vertically within the insulating columns. 
     
     
         19 . The method of  claim 16  wherein filling the encapsulated trenches and vias with metal includes first depositing a conformal metal liner and then depositing a bulk metal. 
     
     
         20 . The method of  claim 16  wherein filling the encapsulated trenches and vias with metal forms metal lines directly above filled vias. 
     
     
         21 . The method of  claim 16  wherein patterning the high modulus insulator film uses a dual damascene process that includes first etching trenches followed by etching vias, stopping on the substrate, to create the array of freestanding insulating columns. 
     
     
         22 . The method of  claim 16  wherein patterning the high modulus insulator film uses a dual damascene process that includes first etching vias, stopping on the substrate, and then etching trenches to create the array of freestanding insulating columns. 
     
     
         23 . The method of  claim 16  wherein patterning the high modulus insulator film uses a dual damascene process in which trenches and vias are aligned and have approximately equal widths. 
     
     
         24 . The method of  claim 16  wherein patterning the high modulus insulator film uses a dual damascene process in which trenches and vias are formed such that the trenches are approximately twice as deep as the vias. 
     
     
         25 . A method of fabricating an integrated circuit interconnect structure on a semiconductor substrate, the method comprising:
 patterning trenches and vias in a high modulus insulator;   forming U-shaped structures containing tapered air gaps; and   filling the trenches and vias to form metal lines and filled vias among the U-shaped structures.   
     
     
         26 . The method of  claim 25  wherein the patterning dielectric U-shaped structures uses a sidewall image transfer technique. 
     
     
         27 . The method of  claim 25  wherein the dielectric U-shaped structures have at least a 4:1 aspect ratio. 
     
     
         28 . The method of  claim 25  wherein at least some of the metal lines are aligned on top of filled vias to form metal interconnect structure elements having a substantially uniform width. 
     
     
         29 . The method of  claim 25  wherein the dielectric U-shaped structures are made of a bi-layer material that includes one or more of SiN, SiC, and SiC x N y  on top of a ULK dielectric.