Decision feedback equalizer with multiple cores for highly-spectrally-efficient communications
Abstract
One or more embodiments describe a decision feedback equalizer with multiple cores for highly spectrally efficient communications. An equalization circuit in a receiver may include a decision feedback equalizer circuit having a first plurality of tap coefficients that are determined based on a cost function that receives as input an error signal that is an inter-symbol-correlated (ISC) signal. The decision feedback equalizer circuit may further include a second plurality of tap coefficients that are determined based on a filter with an ISC response. The cost function may determine the mean square of the error signal. The cost function is constrained or unconstrained. The error signal may represents error caused by a channel. In some embodiments, the ISC signal may be a partial response signal, and the filter with an ISC response may be a partial response filter.
Claims
exact text as granted — not AI-modified1 - 20 . (canceled)
21 . A method comprising:
in a receiver:
receiving a nonlinearly-distorted signal via an analog front-end of said receiver;
generating, by nonlinear distortion modeling circuitry of said receiver, a model of said nonlinear distortion, wherein said model of said nonlinear distortion can be applied to a candidate signal generated in said receiver to distort said candidate signal; and
equalizing, by an equalizer of said receiver, said received nonlinearly distorted signal using said model of nonlinear distortion.
22 . The method of claim 21 , comprising adapting tap coefficients of said equalizer during operation of said receiver.
23 . The method of claim 22 , wherein said adapting is based on a cost function that incorporates the mean square of an error signal.
24 . The method of claim 23 , wherein the cost function is constrained.
25 . The method of claim 22 , wherein said adapting is based on a symbol error rate measured in said receiver.
26 . The method of claim 21 , wherein said model of nonlinear distortion is represented as a polynomial expression.
27 . The method of claim 21 , wherein said model of nonlinear distortion is represented as an exponential expression.
28 . The method of claim 21 , comprising performing sequence estimation to recover symbols carried in said received nonlinearly-distorted signals.
29 . The method of claim 28 , comprising adapting tap coefficients of said equalizer based on an output of said sequence estimation.
30 . The method of claim 21 , wherein said equalizer is a decision feedback equalizer.
31 . A receiver comprising:
front-end circuitry operable to receive a nonlinearly-distorted signal; nonlinear distortion modeling circuitry operable to generate a model of said nonlinear distortion, wherein said model of said nonlinear distortion can be applied to a candidate signal generated in said receiver to distort said candidate signal; and equalizer circuitry operable to equalize said received nonlinearly distorted signal using said model of nonlinear distortion.
32 . The receiver of claim 31 , wherein said equalizer circuitry is operable to adapt tap coefficients of said equalizer circuitry during operation of said receiver.
33 . The method of claim 32 , wherein said adaptation is based on a cost function that incorporates the mean square of an error signal.
34 . The receiver of claim 33 , wherein the cost function is constrained.
35 . The receiver of claim 32 , wherein said adaptation is based on a symbol error rate measured in said receiver.
36 . The receiver of claim 31 , wherein said model of nonlinear distortion is represented as a polynomial expression.
37 . The receiver of claim 31 , wherein said model of nonlinear distortion is represented as an exponential expression.
38 . The receiver of claim 31 , comprising sequence estimation circuitry operable to perform sequence estimation to recover symbols carried in said received nonlinearly-distorted signals.
39 . The receiver of claim 38 , wherein said equalizer circuitry is operable to adapt tap coefficients of said equalizer circuitry based on an output of said sequence estimation circuit.
40 . The receiver of claim 31 , wherein said equalizer circuitry is operable to perform decision feedback equalization.Join the waitlist — get patent alerts
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