Method of di/dt current sensing

Abstract

An integrated circuit package includes a power circuit having a plurality of transistors which form part of a main current loop of the power circuit, the plurality of transistors arranged in one or more layers of the integrated circuit package. The integrated circuit package further includes a conductive loop electrically decoupled from the plurality of transistors. The conductive loop is spaced apart from the plurality of transistors and in close enough proximity to at least part of the main current loop so that the conductive loop is operable to generate a voltage proportional to an electromagnetic field generated responsive to a change in current in the main current loop. A method of fabricating the integrated circuit package is also provided.

What is claimed is: 
     
         1 . An integrated circuit package, comprising:
 a power circuit including a plurality of transistors which form part of a main current loop of the power circuit, the plurality of transistors arranged in one or more layers of the integrated circuit package; and   a conductive loop electrically decoupled from the plurality of transistors, the conductive loop being spaced apart from the plurality of transistors and in close enough proximity to at least part of the main current loop so that the conductive loop is operable to generate a voltage proportional to an electromagnetic field generated responsive to a change in current in the main current loop.   
     
     
         2 . The integrated circuit package of  claim 1 , wherein the conductive loop is arranged within the integrated circuit package in a different layer of the integrated circuit package than the plurality of transistors. 
     
     
         3 . The integrated circuit package of  claim 1 , wherein the conductive loop is attached to an external surface of the integrated circuit package. 
     
     
         4 . The integrated circuit package of  claim 1 , further comprising a first external terminal coupled to one end of the conductive loop and a second external terminal coupled to the other end of the conductive loop, the first and second external terminals providing connection points for the conductive loop at an external surface of the integrated circuit package. 
     
     
         5 . The integrated circuit package of  claim 1 , wherein the power circuit includes a first MOSFET and a second MOSFET, the conductive loop is positioned over at least a portion of the first MOSFET and at least a portion of the second MOSFET, and an insulator layer is interposed between the conductive loop and the first and second MOSFETs. 
     
     
         6 . The integrated circuit package of  claim 5 , wherein the first MOSFET is a high-side MOSFET of a power converter circuit and the second MOSFET is a low-side MOSFET of the power converter circuit. 
     
     
         7 . A method of fabricating an integrated circuit package, comprising:
 arranging a power circuit including a plurality of transistors which form part of a main current loop of the power circuit in one or more layers of the integrated circuit package; and   arranging a conductive loop electrically decoupled from and spaced apart from the plurality of transistors, the conductive loop being arranged in close enough proximity to at least part of the main current loop so that the conductive loop is operable to generate a voltage proportional to an electromagnetic field generated responsive to a change in current in the main current loop.   
     
     
         8 . The method of  claim 7 , further comprising coupling a first external terminal to one end of the conductive loop and a second external terminal to the other end of the conductive loop so that the first and second external terminals provide connection points for the conductive loop at an external surface of the integrated circuit package. 
     
     
         9 . The method of  claim 7 , further comprising:
 arranging the conductive loop over first and second MOSFETs of the power circuit; and interposing an insulator layer between the conductive loop and the first and second MOSFETs.   
     
     
         10 . The method of  claim 9 , further comprising positioning the conductive loop over at least a portion of the first MOSFET and at least a portion of the second MOSFET.