Borderless contact for ultra-thin body devices

Abstract

After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor device located on a top semiconductor layer of a substrate;   a shallow trench isolation structure having a top surface that is recessed below a top surface of said top semiconductor layer;   a dielectric material portion including a first dielectric material, contacting said top surface of said shallow trench isolation structure, and having a first planar top surface;   a contiguous dielectric layer including a second dielectric material that is different from said first dielectric material, contacting said dielectric material portion, and having a second planar top surface extending over said first planar top surface and said semiconductor device;   a contact-level dielectric layer located over said contiguous dielectric layer; and   at least one contact via structure extending through said contact-level dielectric layer and said contiguous dielectric layer and contacting a component of said semiconductor device located above said top surface of said top semiconductor layer.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein said first planar top surface that is located above said top surface of said top semiconductor layer. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein said semiconductor device is a field effect transistor, and said component is a source metal semiconductor alloy portion or a drain metal semiconductor alloy portion comprising a compound of a semiconductor material and a metal. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein said first planar top surface is recessed below a topmost surface of said component. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein said substrate is a semiconductor-on-insulator (SOI) substrate that includes a stack, from bottom to top, of a handle substrate, a buried insulator layer, and said top semiconductor layer. 
     
     
         6 . The semiconductor structure of  claim 5 , wherein said shallow trench isolation structure is located in a lower portion of a shallow trench extended through said top semiconductor layer, said buried insulator layer, and an upper portion of said handle substrate, and wherein a portion of said dielectric material portion is located in an upper portion of said shallow trench. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein said top surface of said shallow trench isolation layer is located between a top surface and a bottom surface of said buried insulator layer. 
     
     
         8 . The semiconductor structure of  claim 6 , wherein said top surface of said shallow trench isolation layer is located below a top surface of said handle substrate. 
     
     
         9 . The semiconductor structure of  claim 3 , wherein said field effect transistor comprises:
 a gate structure located over a body region of said top semiconductor layer;   planar source/drain regions located within portions of said top semiconductor layer on opposite sides of said gate structure;   raised source/drain regions located on said planar source/drain regions; and   source/drain metal semiconductor alloy regions located on said raised source/drain regions.   
     
     
         10 . The semiconductor structure of  claim 9 , wherein said first planar top surface is located between said top surface of the top semiconductor layer and top surfaces of said source/drain metal semiconductor alloy regions. 
     
     
         11 . The semiconductor structure of  claim 9 , wherein said gate structure comprises a vertical stack, from bottom to top, of a gate dielectric, a gate conductor, and a gate cap dielectric, wherein a top surface of said gate cap dielectric is located above said source/drain metal semiconductor alloy regions. 
     
     
         12 . The semiconductor structure of  claim 11 , wherein said second planar top surface of is located above said top surface of said gate cap dielectric. 
     
     
         13 . The semiconductor structure of  claim 1 , wherein said at least one contact via structure is in direct contact with a portion of said dielectric material portion and said component. 
     
     
         14 . The semiconductor structure of  claim 1 , wherein each of said dielectric material portion and said contiguous dielectric layer comprises silicon nitride, silicon oxide, or a dielectric metal oxide having a dielectric constant greater than 8.0. 
     
     
         15 . The semiconductor structure of  claim 1 , wherein said contiguous dielectric layer comprises a stress-generating material.