Semiconductor device

Abstract

In a multichip thin package requiring a thickness of submillimeter region, it is difficult to thin the package if the chips are mounted over a usual die pad. According to a technique of the present application, in a manufacturing method of a semiconductor device of a thin resin sealed multichip rectangular package having wire connection between the chips, at least one chip is fixed to a die pad thinned more than a die pad support lead, the die pad is supported by die pad support leads arranged to respectively connect a pair of long sides of the rectangle, and sealing resin is introduced from one side of the pair of long sides when resin molding is performed.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a die pad;   a first adhesive layer arranged on the die pad;   a second adhesive layer spaced from the die pad and the first adhesive layer in plan view;   a first chip arranged on the first adhesive layer;   a second chip arranged on the second adhesive layer and also spaced from the die pad, the first adhesive layer, and the first chip in plan view; and   a sealing body sealing the first chip and the second chip such that a part of the die pad and a part of the second adhesive layer are exposed from the sealing body.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein a thickness of the first chip is less than a thickness of the second chip. 
     
     
         23 . The semiconductor device according to  claim 22 ,
 wherein the first chip is a silicon semiconductor chip, and   wherein the second chip is a compound semiconductor chip.   
     
     
         24 . The semiconductor device according to  claim 22 ,
 wherein the first chip includes a substrate comprised of silicon, and   wherein the second chip includes a substrate comprised of one of GaAs, GaN, AlGaAs, SiC, InSb and InP.   
     
     
         25 . The semiconductor device according to  claim 21 ,
 wherein the first chip is a silicon semiconductor chip, and   wherein the second chip is a compound semiconductor chip.   
     
     
         26 . The semiconductor device according to  claim 21 ,
 wherein the first chip includes a substrate comprised of silicon, and   wherein the second chip includes a substrate comprised of one of GaAs, GaN, AlGaAs, SiC, InSb and InP.   
     
     
         27 . The semiconductor device according to  claim 21 , wherein a die pad support lead connected with the die pad is arranged between the die pad and the second chip in plan view. 
     
     
         28 . The semiconductor device according to  claim 27 , wherein a thickness of the die pad is less than a thickness of the die pad support lead. 
     
     
         29 . The semiconductor device according to  claim 21 , wherein a shape of the sealing body in plan view is a rectangle. 
     
     
         30 . The semiconductor device according to  claim 21 ,
 wherein the die pad is arranged between a first lead and a second lead,   wherein the first chip is electrically connected with the first lead via a first wire,   wherein the second chip is electrically connected with the second lead via a second wire,   wherein the first chip is electrically connected with the second chip via a third wire, and   wherein the first wire, the second wire, the third wire, the first chip, and the second chip are sealed with the sealing body, such that a part of the first lead, a part of the second lead, the part of the die pad, and the part of the second adhesive layer are exposed from the sealing body.   
     
     
         31 . The semiconductor device according to  claim 30 , wherein the first wire, the second wire, the third wire, the first chip, and the second chip are sealed with the sealing body, such that the part of the first lead, the part of the second lead, the part of the die pad, and the part of the second adhesive layer are exposed from a first surface of the sealing body. 
     
     
         32 . The semiconductor device according to  claim 21 , wherein the first chip and the second chip are sealed with the sealing body, such that the part of the die pad and the part of the second adhesive layer are exposed from a first surface of the sealing body. 
     
     
         33 . The semiconductor device according to  claim 21 , wherein a combined height of the die pad, the first adhesive layer, and the first chip is greater than a combined height of the second adhesive layer and the second chip. 
     
     
         34 . The semiconductor device according to  claim 21 , wherein the second chip has no underlying die pad.