Clock synchronized non-volatile memory device

Abstract

A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives commands including read and program commands. The data register receives from and outputs data to outside. The control circuit reads operation steps from memory used to control the apparatus. The control circuit, responsive to the read command, controls reading data from the memory cells, storing read data to the data register, and outputting read data via the other terminal, not the command terminal, based on the clock signal. The control circuit, responsive to the program command, controls receiving data via the other terminal, not the command terminal, based on the clock signal, storing received data to the data register and writing received data to the memory cells.

1 . A nonvolatile memory apparatus, comprising:
 a nonvolatile memory array;   a plurality of terminals including a command terminal, a clock terminal and another terminal; and   a control circuit,   wherein said command terminal is capable of receiving commands which include a read command and a write command,   wherein said clock terminal is capable of receiving a clock signal,   wherein said nonvolatile memory array includes a plurality of word lines each of which coupled to a plurality of nonvolatile memory cells,   wherein in an operation in response to said read command received from said command terminal, said control circuit controls to selecting at least one word line, to supplying a read voltage to said at least one word line, to reading data from ones of said nonvolatile memory cells coupled to said at least one word line, and to outputting data via said other terminal in response to said clock signal,   wherein in an operation in response to said write command received from said command terminal, said control circuit controls to receiving data via said other terminal in response to said clock signal, to selecting at least one word line, to supplying a program voltage to said at least one word line for writing data to at least one nonvolatile memory cell coupled to said at least one word line, to supplying a verify voltage to said at least one word line for checking whether said at least one nonvolatile memory cell is completed writing data or not, and to repeating supplying said program voltage and supplying said verify voltage to said at least one word line until said at least one nonvolatile memory cell is completed writing data,   wherein each of said nonvolatile memory cells has a threshold voltage within one of a plurality of threshold voltage ranges,   wherein said plurality of threshold voltage ranges comprise a threshold voltage range indicating an erase state and a threshold voltage range indicating a program state,   wherein said control circuit controls moving said threshold voltages of ones of said nonvolatile memory cells coupled to said at least one word line to within said threshold voltage range indicating said erase state in said operation in response to an erase command received, and   wherein said control circuit controls moving said threshold voltage of said nonvolatile memory cell coupled to said at least one word line to within said threshold voltage range indicating said program state and staying said threshold voltages of remaining memory cells of ones of said nonvolatile memory cells coupled to said at least one word line within said threshold voltage range indicating said erase state, in said operation in response to said program command.   
     
     
         2 . The apparatus of  claim 1  further comprising:
 a logic circuit in electrical communication with the control circuit and the other terminal, wherein during an operation in response to said read command received, data is output from the logic circuit via said other terminal except said command terminal in response to said clock signal. 
 
     
     
         3 . The apparatus of  claim 2 , wherein during said write command the control circuit controls to receiving data at the logic circuit via said other terminal except said command terminal in response to said clock signal. 
     
     
         4 . The apparatus of  claim 2 , wherein in an operation in response to said erase command received, said control circuit controls to selecting at least one word line, and to supplying an erase voltage to said at least one word line for erasing data into ones of said nonvolatile memory cells coupled to said at least one word line, wherein said erase voltage is within the threshold voltage ranging indicating an erase state.