Three-Dimensional Flash NOR Memory System With Configurable Pins

Abstract

A three-dimensional NOR flash memory system is disclosed. The system optionally comprises configurable standard pins, a configurable output buffer, and a configurable input buffer.

What is claimed is: 
     
         1 . A three-dimensional memory system, comprising:
 a plurality of standard pins coupled to a logic circuit;   the logic circuit comprising a control block;   a memory array;   the plurality of pins configurable by the control block to perform a function chosen from a plurality of functions, wherein one of the plurality of functions is accessing the array.   
     
     
         2 . The system of  claim 1 , wherein one of the functions is providing a standard serial memory interface to the array. 
     
     
         3 . The system of  claim 1 , wherein one of the functions is providing a non-standard serial memory interface to the array. 
     
     
         4 . The system of  claim 1 , wherein one of the functions is providing a standard parallel interface to the array. 
     
     
         5 . The system of  claim 1 , wherein one of the functions is providing a non-standard parallel interface to the array. 
     
     
         6 . The system of  claim 1 , wherein one of the functions is providing a miled serial and parallel interface to the array. 
     
     
         7 . The system of  claim 1 , wherein one of the functions is providing a testing function. 
     
     
         8 . The system of  claim 1 , wherein one of the functions is providing access to internal signals of the memory system. 
     
     
         9 . The system of  claim 1 , wherein the control block is controlled by a control pin. 
     
     
         10 . The system of  claim 1 , wherein the control block is controlled by a controller. 
     
     
         11 . The system of  claim 1 , wherein at least one pin is coupled to the logic circuit through a TSV. 
     
     
         12 . The system of  claim 1 , wherein at least one pin is coupled to the logic circuit through a microbump. 
     
     
         13 . The system of  claim 1 , wherein at least one pin is coupled to the logic circuit through a bondwire. 
     
     
         14 . The system of  claim 1 , wherein the array is a SuperFlash array. 
     
     
         15 . The system of  claim 1 , wherein the standard pin is a serial SPI or SQI pin. 
     
     
         16 . The system of  claim 1 , wherein the standard pin is a parallel MPF pin. 
     
     
         17 . The system of  claim 1 , wherein the interface pin is deconfigured without ESD or with a smaller ESD structure. 
     
     
         18 . The system of  claim 1 , wherein the output pin is configured optimizing for 3D smaller load performance. 
     
     
         19 . The system of  claim 1 , wherein the input pin is configured optimizing for 3D performance. 
     
     
         20 . The system of  claim 1  further comprising data bandwidth that is more than the standard NOR memory I/O bandwidth. 
     
     
         21 . The system of  claim 1  further comprising a microcontroller. 
     
     
         22 . A three-dimensional memory system, comprising:
 a plurality of pins coupled to a logic circuit;   the logic circuit comprising a control block;   a memory array; and   the plurality of pins configurable by the control block to perform a first function or a second function, wherein the first function is providing addresses to the memory array and the second function is accessing internal signals of the memory system.   
     
     
         23 . The system of  claim 22 , wherein the internal signals comprise internal address signals. 
     
     
         24 . The system of  claim 22 , wherein the internal signals comprise internal input-output signals. 
     
     
         25 . The system of  claim 22 , wherein the internal signals comprise internal control signals. 
     
     
         26 . The system of  claim 22 , wherein the control block is controlled by a control pin. 
     
     
         27 . The system of  claim 22 , wherein the control block is controlled by a controller. 
     
     
         28 . The system of  claim 22 , wherein at least one pin is coupled to the logic circuit through a TSV. 
     
     
         29 . The system of  claim 22 , wherein the array is a SuperFlash array. 
     
     
         30 . The system of  claim 22 , wherein the standard pin is a serial SPI or SQI pin. 
     
     
         31 . The system of  claim 22 , wherein the standard pin is a parallel MPF pin. 
     
     
         32 . The system of  claim 22 , wherein the interface pin is deconfigured without ESD or with a smaller ESD structure. 
     
     
         33 . The system of  claim 22 , wherein the output pin is configured optimizing for 3D smaller load performance. 
     
     
         34 . The system of  claim 22 , wherein the input pin is configured optimizing for 3D performance. 
     
     
         35 . The system of  claim 22  further comprising I/O data bandwidth that is more than the standard NOR memory I/O bandwidth. 
     
     
         36 . The system of  claim 22  further comprising a microcontroller. 
     
     
         37 . A memory system, comprising:
 a plurality of pins coupled to a logic circuit;   the logic circuit comprising a control block; and   a memory array;   wherein the plurality of pins are configurable by the control block to perform a first function or a second function, wherein the first function is providing a serial interface to the memory array and the second function is providing a parallel interface to the memory array.   
     
     
         38 . The system of  claim 37 , wherein the memory array is a two dimensional memory array. 
     
     
         39 . The system of  claim 37 , wherein the memory array is a three dimensional memory array. 
     
     
         40 . The system of  claim 37 , wherein the serial interface is a standard interface. 
     
     
         41 . The system of  claim 37 , wherein the serial interface is a non-standard interface. 
     
     
         42 . The system of  claim 37 , wherein the parallel interface is a standard interface. 
     
     
         43 . The system of  claim 37 , wherein the parallel interface is a non-standard interface. 
     
     
         44 . The system of  claim 38 , wherein the control block is controlled by a control pin. 
     
     
         45 . The system of  claim 38 , wherein the control block is controlled by a controller. 
     
     
         46 . The system of  claim 37 , wherein at least one pin is coupled to the logic circuit through a TSV. 
     
     
         47 . The system of  claim 37 , wherein the array is a SuperFlash array. 
     
     
         48 . The system of  claim 37 , wherein the standard pin is a serial SPI or SQI pin. 
     
     
         49 . The system of  claim 37 , wherein the standard pin is a parallel MPF pin. 
     
     
         50 . The system of  claim 37 , wherein the interface pin is configured without standard ESD or with a smaller non-standard ESD structure. 
     
     
         51 . The system of  claim 37 , wherein the output pin is configured optimizing for smaller non-standard load performance. 
     
     
         52 . The system of  claim 37 , wherein the input pin is configured optimizing for non-standard NOR memory interface performance. 
     
     
         53 . The system of  claim 37  further comprising I/O data bandwidth that is more than the standard NOR memory I/O bandwidth. 
     
     
         54 . The memory system of  claim 37  further comprising a microcontroller. 
     
     
         55 . A three-dimensional memory system, comprising:
 a plurality of standard memory pins coupled to a logic circuit;   a memory array;   the plurality of pins configurable to perform a function chosen from a plurality of functions, wherein one of the plurality of functions is accessing the array.   
     
     
         56 . The system of  claim 55 , wherein one of the functions is providing a standard serial memory interface to the array. 
     
     
         57 . The system of  claim 55  wherein one of the functions is providing a non-standard serial memory interface to the array. 
     
     
         58 . The system of  claim 55 , wherein one of the functions is providing a standard parallel memory interface to the array. 
     
     
         59 . The system of  claim 55 , wherein one of the functions is providing a non-standard parallel memory interface to the array. 
     
     
         60 . The system of  claim 55 , wherein one of the functions is providing a mixed serial and parallel memory interface to the array. 
     
     
         61 . The system of  claim 55 , wherein one of the functions is providing a testing function. 
     
     
         62 . The system of  claim 55 , wherein one of the functions is providing access to internal signals of the memory system. 
     
     
         63 . The system of  claim 55 , wherein at least one pin is coupled to the logic circuit through a TSV. 
     
     
         64 . The system of  claim 55 , wherein at least one pin is coupled to the logic circuit through a microbump. 
     
     
         65 . The system of  claim 55 , wherein at least one pin is coupled to the logic circuit through a bondwire. 
     
     
         66 . The system of  claim 55 , wherein the array is a SuperFlash array. 
     
     
         67 . The system of  claim 55 , wherein the standard pin is a serial SPI or SQI pin. 
     
     
         68 . The system of  claim 55 , wherein the standard pin is a parallel MPF pin. 
     
     
         69 . The system of  claim 55 , wherein the interface pin is deconfigured without ESD or with a smaller ESD structure. 
     
     
         70 . The system of  claim 55 , wherein the output pin is configured optimizing for 3D smaller load performance. 
     
     
         71 . The system of  claim 55 , wherein the input pin is configured optimizing for 3D performance. 
     
     
         72 . The system of  claim 55  further comprising I/O data bandwidth that is more than the standard NOR memory I/O bandwidth. 
     
     
         73 . The system of  claim 55  further comprising a microcontroller.