Estimating delay deterioration due to device degradation in integrated circuits

Abstract

A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.

What is claimed is: 
     
         1 . A system for estimating delay deterioration in an integrated circuit comprising:
 a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit;   a netlist generator for generating an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations; and   a timing analyzer for performing a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.   
     
     
         2 . The system of  claim 1 , wherein the at least one characteristic includes threshold-voltage as a function of at least one of a device's operating voltage, operating temperature, on and off duration times and transition slew. 
     
     
         3 . The system of  claim 1 , further including a probability estimator for estimating the probability of failure of the integrated circuit over each of the one or more lifetimes for a given operating specification based on each of the determined circuit path delays. 
     
     
         4 . The system of  claim 1 , wherein the simulation uses a specific pattern representative of a workload to be seen by the integrated circuit. 
     
     
         5 . The system of  claim 1 , wherein the netlist generator generates the end-of-life netlists based on an original netlist file that describes the devices included in the integrated circuit. 
     
     
         6 . The system of  claim 5 , wherein the devices in the integrated circuit include both analog and digital devices. 
     
     
         7 . The system of  claim 5 , wherein the netlist comprises a listing of possible connections between devices and properties of each device. 
     
     
         8 . The system of  claim 7 , wherein the timing analyzer further performs a first timing analysis on the original netlist file. 
     
     
         9 . The system of  claim 8 , wherein the first timing analysis uses the properties of each device to determine nominal circuit path delays at production time. 
     
     
         10 . The system of  claim 8 , wherein the timing analyzer performs timing analyses using static timing analysis that operates on asserted device characteristics presented as single, fixed-point values and provides nominal circuit path delays as single, fixed-point values. 
     
     
         11 . The system of  claim 8 , wherein timing analyzer performs timing analyses using statistical timing analysis that operates on asserted device characteristics presented as a distribution of nominal values for each device and provides nominal circuit path delays as a distribution of values for each device. 
     
     
         12 . A system for estimating delay deterioration in an integrated circuit comprising:
 a degradation estimator for estimating future degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit;   a netlist generator for generating an end-of-life netlist for each of the one or more lifetimes, based on an original netlist file that describes the devices included in the integrated circuit, in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations; and   a timing analyzer for performing a first timing analysis on the original netlist file and one or more second timing analyses on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.   
     
     
         13 . The system of  claim 12 , wherein the at least one characteristic includes threshold-voltage as a function of at least one of a device's operating voltage, operating temperature, on and off duration times and transition slew. 
     
     
         14 . The system of  claim 12 , further including a probability estimator for estimating the probability of failure of the integrated circuit over each of the one or more lifetimes for a given operating specification based on each of the determined circuit path delays. 
     
     
         15 . The system of  claim 12 , wherein the simulation uses a specific pattern representative of a workload to be seen by the integrated circuit. 
     
     
         16 . The system of  claim 12 , wherein the devices in the integrated circuit include both analog and digital devices. 
     
     
         17 . The system of  claim 12 , wherein the netlist comprises a listing of possible connections between devices and properties of each device. 
     
     
         18 . The system of  claim 12 , wherein the first timing analysis uses the properties of each device to determine nominal circuit path delays at production time. 
     
     
         19 . The system of  claim 12 , wherein the timing analyzer performs timing analyses using static timing analysis that operates on asserted device characteristics presented as single, fixed-point values and provides nominal circuit path delays as single, fixed-point values. 
     
     
         20 . The system of  claim 12 , wherein timing analyzer performs timing analyses using statistical timing analysis that operates on asserted device characteristics presented as a distribution of nominal values for each device and provides nominal circuit path delays as a distribution of values for each device.