Novel semiconductor package with through silicon vias

Abstract

The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns.

What is claimed is: 
     
         1 . A method, comprising:
 forming a plurality of trenches in a first side of a first substrate;   filling the trenches with a conductive material;   coupling a second substrate to the first substrate through the first side;   thinning the first substrate from a second side of the first substrate, the second side being opposite the first side, wherein the thinning is performed until the conductive material filling the trenches is exposed;   forming a conductive layer over the second side of the first substrate, wherein the conductive layer is thermal-conductively coupled to the conductive material filling the trenches; and   bonding a chip to the conductive layer.   
     
     
         2 . The method of  claim 1 , wherein the conductive layer is formed as a plurality of conductive contact pads, and wherein the chip is bonded to a first one of the conductive contact pads. 
     
     
         3 . The method of  claim 2 , further comprising: wire bonding the chip with a second one of the conductive pads. 
     
     
         4 . The method of  claim 3 , wherein the bonding comprises bonding a plurality of chips to the conductive layer, wherein the wire bonding comprises wire bonding the plurality of chips to the same second one of the conductive pads. 
     
     
         5 . The method of  claim 4 , wherein the second one of the conductive pads encircles the plurality of chips in a top view. 
     
     
         6 . The method of  claim 2 , wherein the chip includes a light-emitting diode (LED). 
     
     
         7 . The method of  claim 1 , wherein the filling of the trenches is performed such that a portion of the conductive material is disposed outside of the trenches over the first side of the first substrate. 
     
     
         8 . The method of  claim 1 , wherein the coupling of the second substrate comprises attaching the second substrate to the first substrate through a glue layer. 
     
     
         9 . The method of  claim 1 , wherein the second substrate is a glass substrate or a metal substrate. 
     
     
         10 . The method of  claim 1 , wherein the first substrate is a silicon substrate or a silicon-on-insulator (SOI) substrate. 
     
     
         11 . A method, comprising:
 forming a plurality of recesses in a first side of a first substrate, the first substrate being a silicon substrate or a silicon-on-insulator (SOI) substrate;   forming conductive plugs by filling the recesses with a metal material;   attaching, via a glue layer, a second substrate to the first side of the first substrate, wherein the second substrate is a glass substrate or a metal substrate;   grinding the first substrate from a second side of the first substrate opposite the first side, wherein the grinding is performed until the conductive plugs are exposed;   forming at least a first conductive pad and a second conductive pad over the second side of the first substrate, wherein the first conductive pad is thermal-conductively coupled to a first subset of the conductive plugs, and wherein the second conductive pad is thermal-conductively coupled to a second subset of the conductive plugs;   bonding a first side of a semiconductor chip to the first conductive pad; and   wire bonding a second side of the semiconductor chip to the second conductive pad.   
     
     
         12 . The method of  claim 11 , wherein:
 the forming of the first conductive pad comprises forming a plurality of additional first conductive pads;   the bonding comprises bonding a plurality of additional semiconductor chips to the additional first conductive pads through their first sides, respectively; and   the wire bonding comprises wire bonding a second side of each of the additional semiconductor chips to the second conductive pad.   
     
     
         13 . The method of  claim 11 , wherein the semiconductor chip and the additional semiconductor chips are circumferentially surrounded by the second contact pad in a top view. 
     
     
         14 . A method of creating a semiconductor package utilizing through silicon plugs, comprising:
 providing a first substrate;   forming through silicon plugs in the first substrate extending from a first surface of the first substrate, wherein the through silicon plugs are lined with an isolation layer and a first copper barrier layer, and wherein the through silicon plugs are filled with a first copper layer;   removing excess silicon from the first substrate to expose first ends of through silicon plugs buried in the first substrate;   forming a second copper layer on the first ends of through silicon plugs, wherein a second copper barrier layer is deposited on the first ends of the through silicon plugs before forming the second copper layer; and   placing a semiconductor chip on the second copper layer.   
     
     
         15 . The method of  claim 14 , further comprising:
 depositing a diffusion barrier layer on the second copper layer after the second copper layer is formed;   depositing a eutectic bonding layer on the diffusion barrier layer; and   placing the semiconductor chip directly on eutectic bonding.   
     
     
         16 . The method of  claim 14 , wherein a height of the through silicon plugs is between about 20 μm to about 200 μm. 
     
     
         17 . The method of  claim 14 , the first substrate is patterned by using dry film resists after the through silicon plugs have been opened and before the through silicon plugs have been filled to prevent wet photoresist from contaminating surfaces in openings of through silicon plugs. 
     
     
         18 . The method of  claim 14 , wherein the copper layer has a thickness less than about 30 μm. 
     
     
         19 . The method of  claim 14 , wherein the first and second copper barrier layers are made of one or more materials selected from a group consisting of Ti, TiN, Ta, TaN, CoW, and a combination of the above mentioned films. 
     
     
         20 . The method of  claim 14 , wherein the first copper layer and the second copper layer are deposited by one or more copper plating processes.