Semiconductor device

Abstract

A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor substrate having at least first and second regions;   a memory capacitor over the first region, the memory capacitor comprising:
 a first lower electrode; and 
 a first dielectric film covering inner and outer surfaces of the first lower electrode; and 
   a first compensation capacitor over the second region, the first compensation capacitor comprising:
 a second lower electrode, the first dielectric film covering an inner surface of the second lower electrode; and 
 a first insulating film covering an outer surface of the second lower electrode. 
   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 the memory capacitor further comprises:
 a first upper electrode covering the first dielectric film, and 
   the first compensation capacitor comprises:
 a second upper electrode covering the first dielectric film. 
   
     
     
         3 . The semiconductor device according to  claim 2 , wherein
 the first compensation capacitor further comprises:
 a third lower electrode having inner and outer surfaces, the inner surface of the third lower electrode being covered by the first dielectric film, the outer surface of the third lower electrode being covered by the first insulating film, and the third lower electrode being electrically connected to the second lower electrode. 
   
     
     
         4 . The semiconductor device according to  claim 2 , further comprising:
 a first wire electrically connected to the first upper electrode; and   a second wire electrically connected to the second upper electrode.   
     
     
         5 . The semiconductor device according to  claim 2 , further comprising:
 a second compensation capacitor over the second region, the second compensation capacitor comprising:
 a fourth lower electrode having inner and outer surfaces, the outer surface of the fourth lower electrode being covered by the first insulating film; 
 a second dielectric film covering the inner surface of the fourth lower electrode; and 
 a third upper electrode covering the second dielectric film. 
   
     
     
         6 . The semiconductor device according to  claim 5 , wherein the second lower electrode is electrically connected to the fourth lower electrode. 
     
     
         7 . The semiconductor device according to  claim 6 , further comprising:
 a first pad over the second region, the second and fourth lower electrodes extending vertically from the first pad.   
     
     
         8 . The semiconductor device according to  claim 6 , further comprising:
 a third wire electrically connected to the second upper electrode; and   a fourth wire electrically connected to the third upper electrode.   
     
     
         9 . The semiconductor device according to  claim 5 , wherein the second upper electrode is electrically connected to the third upper electrode. 
     
     
         10 . The semiconductor device according to  claim 9 , further comprising:
 a fifth wire electrically connected to the second lower electrode; and   a sixth wire electrically connected to the fourth lower electrode.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein the first compensation capacitor further comprises:
 a second pad over the second region, the second pad being electrically connected to the fifth wire, and the second lower electrode extending vertically from the second pad, and   the second compensation capacitor further comprises:   a third pad over the second region, the third pad being electrically connected to the sixth wire, the third pad being electrically connected to the sixth wire, and the fourth lower electrode extending vertically from the third pad.   
     
     
         12 . The semiconductor device according to  claim 5 , wherein the second upper electrode is electrically connected to the fourth lower electrode. 
     
     
         13 . The semiconductor device according to  claim 12 , wherein the second compensation capacitor further comprises:
 a fourth pad over the second region, the fourth lower electrode extending vertically from the fourth pad, and   the semiconductor device further comprises:   a seventh wire electrically connects the second upper electrode and the fourth pad.   
     
     
         14 . The semiconductor device according to  claim 1 , wherein the semiconductor substrate has a third region other than the first and second regions, and the semiconductor device further comprises:
 a fifth lower electrode over the third region, the first dielectric film covering an inner surface of the fifth lower electrode, and the fifth lower electrode surrounds the first region in plan view.   
     
     
         15 . The semiconductor device according to  claim 1 , wherein the first and second lower electrodes have a cylindrical shape. 
     
     
         16 . The semiconductor device according to  claim 1 , wherein the first and second lower electrodes extend in a first direction vertical to the semiconductor substrate. 
     
     
         17 . The semiconductor device according to  claim 2 , further comprising:
 a gate electrode structure over the first region;   a second insulating film covering at least the gate electrode structure and the semiconductor substrate; and   a first purity layer in the first region, the first impurity layer being positioned adjacent to an upper surface of the semiconductor substrate and the gate electrode structure, wherein the memory capacitor is positioned over the second insulating film, and the first lower electrode is electrically connected to the first impurity layer.   
     
     
         18 . A semiconductor device comprising:
 a first insulating film;   a first lower electrode over the first insulating film;   a second lower electrode over the first insulating film, the second lower electrode being positioned adjacent to the first lower electrode;   a first dielectric film covering an inner surface of the first lower electrode and an inner surface of the second lower electrode;   a first upper electrode covering the first dielectric film;   a second upper electrode covering the first dielectric film; and   a second insulating film covering outer surfaces of the first and second lower electrodes,   wherein one of the first lower electrode and the first upper electrode is electrically connected to one of the second lower electrode and the second upper electrode.   
     
     
         19 . The semiconductor device according to  claim 18 , further comprising:
 a third lower electrode over the first insulating film, the third lower electrode being positioned adjacent to the second lower electrode;   a second dielectric film covering an inner surface of the third lower electrode, an outer surface of the lower electrode being covered by the second insulating film; and   
       a third upper electrode covering the second dielectric film,
 wherein one of the second lower electrode and the second upper electrode is electrically connected to one of the third lower electrode and the third upper electrode.