Finfet with merge-free fins

Abstract

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

1 . A semiconductor device having first and second non-gate regions, comprising:
 an active semiconductor layer disposed on an insulation layer;   a gate pocket through the active semiconductor layer and the insulation layer, the gate pocket defining a recessed gate insulation region between the first and second non-gate regions; and   a plurality of fins supported by walls of the gate pocket,   wherein a portion of the recessed gate insulation region located beneath the plurality of fins defines a void between each fin among the plurality of fins and the recessed gate insulation region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the recessed gate insulation region extends below the insulation layer at a predetermined depth. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the gate pocket has a depth that reaches the recess gate insulation region. 
     
     
         4 . The semiconductor device of  claim 3 , further comprising arranging the plurality of fins sequentially in the gate pocket. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the gate insulation layer extends along a first direction to define a gate length, and each fin among the plurality of fins extends along the first direction to define a fin length not exceeding the gate length. 
     
     
         6 . The semiconductor device  claim 5 , further comprising a gate stack in the gate pocket to cover the plurality of fins. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the plurality of fins comprises nanowires.