Memory Arrays and Methods of Forming Memory Cells

Abstract

Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.

1 - 31 . (canceled) 
     
     
         32 : A method of forming a plurality of memory cells and select devices, comprising:
 forming a stack which comprises, in ascending order, a homogeneous n-type doped region, a p-type doped region and an ovonic material;   patterning the stack into rails which extend along a first direction and which are spaced from one another by first trenches;   patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction; the patterning forming second trenches which extend along a second direction that intersects the first direction; the p-type doped region and the segments of the homogeneous n-type doped region being incorporated into vertical select devices within the pillars; and   forming second electrically conductive lines over the ovonic material, with the second electrically conductive lines extending along the second direction; the second electrically conductive lines interconnecting the pillars along the second direction.   
     
     
         33 : The method of  claim 32  wherein vertical select devices are diodes. 
     
     
         34 : The method of  claim 32  wherein the p-type doped region is a first p-type doped region, and wherein a second p-type doped region is beneath the homogeneous n-type doped region. 
     
     
         35 : The method of  claim 32  wherein the second direction is orthogonal to the first direction, and wherein a vertical direction of the vertical select devices is orthogonal to both of the first and second directions. 
     
     
         36 : The method of  claim 32  wherein the ovonic material is directly against the p-type doped region. 
     
     
         37 : The method of  claim 32  wherein the ovonic material is spaced from the p-type doped region by one or more intervening materials. 
     
     
         38 : The method of  claim 32  wherein the ovonic material is spaced from the p-type doped region by at least a heater material. 
     
     
         39 : A method of forming a plurality of memory cells, comprising:
 forming a stack over a semiconductor base; the stack comprising, in ascending order from the substrate, a homogeneous n-type doped region, a p-type doped region and an ovonic material;   patterning the stack into rails, with the rails extending along a first direction, the rails being spaced from one another by first trenches;   patterning the rails into pillars, the patterning into the pillars comprising etching into but not entirely through the homogeneous n-type doped region to form a portion of the homogeneous n-type doped region into segments within the pillars, and to leave some of the homogeneous n-type doped region as first conductive lines interconnecting the pillars along the first direction; the patterning forming second trenches which extend along a second direction that intersects the first direction; the p-type doped region and the segments of the homogeneous n-type doped region being incorporated into vertical select devices within the pillars; and   forming second electrically conductive lines over the ovonic material, with the second electrically conductive lines extending along the second direction; the second electrically conductive lines interconnecting the pillars along the second direction.   
     
     
         40 : The method of  claim 39  wherein vertical select devices are diodes. 
     
     
         41 : The method of  claim 39  wherein the p-type doped region is a first p-type doped region, and wherein a second p-type doped region is beneath the homogeneous n-type doped region. 
     
     
         42 : The method of  claim 39  wherein the second direction is orthogonal to the first direction, and wherein a vertical direction of the vertical select devices is orthogonal to both of the first and second directions. 
     
     
         43 : A memory array, comprising:
 first electrically conductive lines, the first electrically conductive lines being n-type doped regions of semiconductor material and extending along a first direction;   pillars over the first conductive lines; the pillars comprising mesas of the n-type doped regions of the semiconductor material extending upwardly from the electrically conductive lines, comprising carbon-containing barrier material over the semiconductor material of the mesas, comprising p-type doped regions over the barrier material, and comprising ovonic material over the p-type doped regions; wherein a common, continuous and homogenous n-type doped semiconductor material comprises both the n-type doped regions of the first electrically conductive lines and the mesas of the n-type doped regions; the p-type doped regions and the mesas of the n-type doped regions being incorporated into vertical select devices within the pillars; and   second electrically conductive lines over the ovonic material; the second electrically conductive lines extending along a second direction that intersects the first direction; the second electrically conductive lines interconnecting the pillars along the second direction.   
     
     
         44 : The memory array of  claim 43  wherein the second direction is orthogonal to the first direction, and wherein a vertical direction of the vertical select devices is orthogonal to both of the first and second directions. 
     
     
         45 : The memory array of  claim 43  further comprising electrically conductive capping material within the pillars and over the ovonic material. 
     
     
         46 : The memory array of  claim 45  wherein the electrically conductive capping material comprises titanium nitride. 
     
     
         47 : The memory array of  claim 43  further comprising heater material between the ovonic material and the p-type doped regions of the pillars.