Packaging substrate and fabrication method thereof

Abstract

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

What is claimed is: 
     
         1 . A packaging substrate, comprising:
 a dielectric layer having opposite first and second surfaces;   a first circuit layer embedded in the first surface of the dielectric layer and having a surface exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; and   a plurality of conductive bumps formed on the first conductive pads and protruding above the first surface of the dielectric layer.   
     
     
         2 . The substrate of  claim 1 , wherein the surface of the first circuit layer is flush with or lower than the first surface of the dielectric layer. 
     
     
         3 . The substrate of  claim 1 , further comprising an insulating layer formed on the first surface of the dielectric layer and the surface of the first circuit layer and having a plurality of openings for exposing the conductive bumps. 
     
     
         4 . The substrate of  claim 1 , further comprising a second circuit layer formed on the second surface of the dielectric layer. 
     
     
         5 . The substrate of  claim 4 , further comprising a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. 
     
     
         6 . The substrate of  claim 4 , further comprising an insulating layer formed on the second surface of the dielectric layer and the second circuit layer and having a plurality of openings for exposing portions of the second circuit layer. 
     
     
         7 . The substrate of  claim 1 , wherein the conductive bumps are less, equal to or greater in width than the first conductive pads. 
     
     
         8 . The substrate of  claim 1 , wherein the conductive bumps are made of copper. 
     
     
         9 . A method for fabricating a packaging substrate, comprising the steps of:
 providing a carrier having a first circuit layer formed thereon, wherein the first circuit layer has a plurality of first conductive pads;   forming a dielectric layer on the carrier and the first circuit layer, wherein the dielectric layer has a first surface in contact with and attached to the carrier and a second surface opposite to the first surface;   removing the carrier so as to expose a surface of the first circuit layer from the first surface of the dielectric layer; and   forming on the first conductive pads a plurality of conductive bumps protruding above the first surface of the dielectric layer.   
     
     
         10 . The method of  claim 9 , wherein the surface of the first circuit layer is flush with or lower than the first surface of the dielectric layer. 
     
     
         11 . The method of  claim 9 , wherein the carrier has a conductive layer that allows the first circuit layer to be formed thereon, and the conductive layer is exposed after removing the carrier such that the step of forming the conductive bumps further comprises:
 forming a metal layer on the conductive layer; and   removing portions of the metal layer and the conductive layer under the metal layer so as for the remaining portions of the metal layer and the conductive layer to form the conductive bumps.   
     
     
         12 . The method of  claim 9 , wherein the carrier has a conductive layer that allows the first circuit layer to be formed thereon, and the conductive layer is exposed after removing the carrier such that the step of forming the conductive bumps further comprises:
 forming a resist layer on the conductive layer and forming a plurality of openings in the resist layer corresponding in position to the first conductive pads;   forming a metal layer in the openings of the resist layer; and   removing the resist layer so as for the metal layer to form the conductive bumps.   
     
     
         13 . The method of  claim 9 , wherein the step of forming the conductive bumps further comprises:
 forming a metal layer on the first surface of the dielectric layer and the surface of the first circuit layer; and   removing portions of the metal layer so as for the remaining portions of the metal layer to form the conductive bumps.   
     
     
         14 . The method of  claim 9 , wherein the carrier has a metal layer, and after the carrier is removed, portions of the metal layer are removed so as for the remaining portions of the metal layer to form the conductive bumps. 
     
     
         15 . The method of  claim 9 , further comprising forming an insulating layer on the first surface of the dielectric layer and the surface of the first circuit layer and forming a plurality of openings in the insulating layer for exposing the conductive bumps. 
     
     
         16 . The method of  claim 9 , further comprising forming a second circuit layer on the second surface of the dielectric layer. 
     
     
         17 . The method of  claim 16 , further comprising forming a plurality of conductive vias in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. 
     
     
         18 . The method of  claim 16 , further comprising forming an insulating layer on the second surface of the dielectric layer and the second circuit layer and forming a plurality of openings in the insulating layer for exposing portions of the second circuit layer. 
     
     
         19 . The method of  claim 9 , wherein the conductive bumps are less, equal to or greater in width than the first conductive pads.