Semiconductor isolation structure and method of manufacture

Abstract

A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.

1 . (canceled) 
     
     
         2 . An isolation structure comprising:
 a trench in a first portion of a semiconductor substrate, the trench defining an area between adjacent first semiconductor regions, the first semiconductor regions having a first type of conductivity, each first semiconductor region being adjacent to a second semiconductor region of a vertical access device, the second semiconductor region having a second type of conductivity;   a dielectric liner material formed in the trench of the adjacent first semiconductor regions; and   a dielectric liner material that fills the trench to form at least a portion of an isolation region such that only the dielectric material is provided between the dielectric liner material formed in the trench between the adjacent first semiconductor regions,   wherein the trench extends into a second portion of the semiconductor substrate residing below the first portion, and wherein the isolation region is formed in the second portion of the semiconductor substrate.   
     
     
         3 . The trench isolation structure of  claim 2 , wherein the trench extends beneath adjacent first semiconductor regions. 
     
     
         4 . The trench isolation structure of  claim 2 , wherein the isolation region is formed in the second portion of the semiconductor substrate to extend beneath an adjacent first semiconductor regions. 
     
     
         5 . The isolation structure of  claim 4 , wherein the dielectric liner material is formed in contact with at least a portion of at least one adjacent first semiconductor regions. 
     
     
         6 . The isolation structure of  claim 2 , further comprising a bit line adjacent to and in electrical communication with the second semiconductor region. 
     
     
         7 . The isolation structure of  claim 6 , wherein the bit line is formed such that the bit line is spaced from a junction where the first semiconductor region and the second semiconductor region contact. 
     
     
         8 . The isolation structure of  claim 6 , wherein the dielectric liner material is formed over the bit line. 
     
     
         9 . The isolation structure of  claim 6 , further comprising an intermediary material formed adjacent to the bit line. 
     
     
         10 . The isolation structure of  claim 2 , further comprising:
 a third semiconductor region formed adjacent to the second semiconductor region, the third semiconductor region having a first dopant type;   a gate oxide formed adjacent to the third semiconductor region; and   a word line formed adjacent to the gate oxide.   
     
     
         11 . A memory device comprising:
 a plurality of storage devices; and   an array of vertical access devices, wherein each storage device is coupled to a corresponding vertical access device, the array comprising:   at least one trench in a first portion of a semiconductor substrate, the trench defining an area between adjacent first semiconductor regions of adjacent vertical access devices, the first semiconductor regions being doped to a first type of conductivity;   a dielectric liner material formed in the trench between the adjacent first semiconductor regions; and   an isolation region comprising a dielectric material that fills the trench such that only the dielectric material is provided between the dielectric liner material formed in the trench region between the adjacent first semiconductor regions,   wherein the trench extends into a second portion of the semiconductor substrate residing below the first portion, and wherein the isolation region is formed in the second portion of the semiconductor substrate.   
     
     
         12 . The memory device of  claim 11 , wherein the trench extends beneath adjacent first semiconductor regions. 
     
     
         13 . The memory device of  claim 11 , wherein the isolation region is formed in the second portion of the semiconductor substrate to extend beneath an adjacent first semiconductor regions. 
     
     
         14 . The memory device of  claim 11 , wherein the isolation region is formed in the second portion of the semiconductor substrate to extend beneath an adjacent first semiconductor regions. 
     
     
         15 . The memory device of  claim 13 , wherein the dielectric liner material is formed in contact with at least a portion of at least one adjacent first semiconductor regions. 
     
     
         16 . The memory device of  claim 11 , further comprising a bit line adjacent to and in electrical communication with the second semiconductor region. 
     
     
         17 . The memory device of  claim 16 , wherein the bit line is formed such that the bit line is spaced from a junction where the first semiconductor region and the second semiconductor region contact. 
     
     
         18 . The memory device of  claim 17 , further comprising an intermediary material formed adjacent to the bit line. 
     
     
         19 . The memory device of  claim 11 , further comprising:
 a third semiconductor region formed adjacent to the second semiconductor region, the third semiconductor region having a first dopant type;   a gate oxide formed adjacent to the third semiconductor region; and   a word line formed adjacent to the gate oxide.   
     
     
         20 . A memory device comprising:
 a plurality of storage devices; and   an array of vertical access devices, wherein each storage device is coupled to a corresponding vertical access device, the array comprising:   at least one trench in a first portion of a semiconductor substrate, the trench defining an area between adjacent first semiconductor regions of adjacent vertical access devices, the first semiconductor regions being doped to a first type of conductivity;   a dielectric liner material formed in the trench between the adjacent first semiconductor regions; and   an isolation region comprising a dielectric material that fills the trench such that only the dielectric material is provided between the dielectric liner material formed in the trench region between the adjacent first semiconductor regions,   wherein the trench extends into a second portion of the semiconductor substrate residing below the first portion, wherein the isolation region is formed in the second portion of the semiconductor substrate, and wherein the isolation region extends beneath an adjacent first semiconductor regions such that it contacts an adjacent isolation region.