Method for manufacturing metal-insulator-metal capacitor structure
Abstract
A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for manufacturing a MIM capacitor, comprising:
forming a first opening in a first dielectric layer; filling a first damascene electrode layer in the first opening; forming an insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer; forming a second dielectric layer on the insulating barrier layer; forming a second opening and a third opening in the second dielectric layer, the second opening and the third opening being located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom; removing the insulating barrier layer in the third opening to expose a portion of the first damascene electrode layer; and forming a second damascene electrode layer in the second opening to be contacted with the insulating barrier layer and forming a dual damascene structure in the third opening to be contacted with the first damascene electrode layer.
2 . The method as claimed in claim 1 , wherein the step of filling the first damascene electrode layer in the first opening comprises:
forming a metal layer on the first dielectric layer and filling the metal layer into the first opening; and removing a portion of the metal layer outside the first opening to form the first damascene electrode layer.
3 . The method as claimed in claim 2 , wherein a chemical mechanical polishing process is applied to remove the portion of the metal layer outside the first opening to form the first damascene electrode layer.
4 . The method as claimed in claim 2 , wherein the metal layer is a copper layer.
5 . The method as claimed in claim 1 , wherein the step of forming the insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer comprises: forming the insulating barrier layer in a single layer structure, and wherein a material of the insulating barrier layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON).
6 . The method as claimed in claim 1 , wherein the step of forming the insulating barrier layer to cover the first dielectric layer and the first damascene electrode layer comprises of forming the insulating barrier layer in a multilayer structure.
7 . The method as claimed in claim 6 , wherein forming the insulating barrier layer in the multilayer structure comprises:
forming a first insulating layer on the first dielectric layer, and wherein a material of the first insulating layer is selected from a group consisting of silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON); and forming a second insulating layer on the first insulating layer, and wherein a material of the second insulating layer is selected from a group consisting of undoped silicate glass (USG), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ) and aluminum oxide (Al 2 O 3 ).
8 . The method as claimed in claim 1 , wherein forming the third opening in the second dielectric layer comprising: forming at least one via; and
forming one trench located above and communicated with the at least one via.
9 . The method as claimed in claim 8 , wherein the third opening is formed by a trench first process, a via first process or a self-aligned process.
10 . The method as claimed in claim 1 , wherein the step of removing the insulating barrier layer in the third opening to expose the portion of the first damascene electrode layer comprises:
forming a patterned mask layer on the second dielectric layer to cover the second opening and to expose the third opening; removing the portion of the insulating barrier layer exposed from the patterned mask; and removing the patterned mask layer.
11 . The method as claimed in claim 1 , wherein the step of forming a second damascene electrode layer in the second opening and forming a dual damascene structure in the third opening comprises:
forming a metal layer on the second dielectric layer and filling the metal layer into the second opening to be contacted with the insulating barrier layer and into the third opening to be contacted with the first damascene electrode layer; and removing a portion of the metal layer outside the second opening and the third opening to form the second damascene electrode layer and the dual damascene structure.
12 . The method as claimed in claim 11 , wherein a chemical mechanical polishing process is applied to remove the portion of the metal layer outside the second opening and the third opening to form the second damascene electrode layer and the dual damascene structure.
13 . The method as claimed in claim 11 , wherein the metal layer is a copper layer.Join the waitlist — get patent alerts
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