Method of forming and structure of a non-volatile memory cell

Abstract

A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process.

What is claimed is: 
     
         1 . A method of forming a non-volatile memory cell comprising:
 defining an active region which comprises a select transistor region and a storage transistor region;   forming a well on a substrate;   forming a stacked layer comprising a bottom dielectric layer, a charge trapping layer and a top dielectric layer;   etching the top dielectric layer in the select transistor region;   forming a select gate on the select transistor region and a memory gate on the storage transistor region; and   forming a plurality of source/drain doped regions.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a plurality of lightly doped region regions.   
     
     
         3 . The method of  claim 1 , wherein the step of defining the active region comprises a step of forming isolations on the substrate. 
     
     
         4 . The method of  claim 1 , wherein the step of forming the well comprises a step of implanting impurities on the substrate. 
     
     
         5 . The method of  claim 1 , wherein step of forming the plurality of lightly doped region regions comprises a step of implanting ions on the well to form four lightly doped regions on the well and each formed between a corresponding bottom dielectric layer and a corresponding source/drain doped region. 
     
     
         6 . The method of  claim 1 , further comprising:
 implanting impurities on the substrate to form a deep well between the substrate and the well.   
     
     
         7 . The method of  claim 6 , wherein the deep well is a deep N-well. 
     
     
         8 . The method of  claim 1 , further comprising:
 implanting impurities on the substrate to form a barrier layer between the substrate and the well.   
     
     
         9 . The method of  claim 8 , wherein the barrier layer is an N-barrier layer. 
     
     
         10 . The method of  claim 1 , wherein a length of the select gate is greater than or equal to a length of the memory gate. 
     
     
         11 . The method of  claim 1 , wherein the first charge trapping layer and the second charge trapping layer are composed of silicon nitride. 
     
     
         12 . The method of  claim 1 , wherein the first charge trapping layer and the second charge trapping layer are composed of silicon oxynitride. 
     
     
         13 . The method of  claim 1 , wherein the substrate is a P-substrate, the well is an N-well, and the source/drain doped regions are P+ doped regions.