Finfet with merge-free fins

Abstract

A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.

1 . A method of forming a semiconductor device having first and second non-gate regions, the method comprising:
 forming an active semiconductor layer disposed on an insulation layer;   forming a gate pocket through the active semiconductor layer and the insulation layer to define a recessed gate insulation region between the first and second non-gate regions;   forming a plurality of fins supported by walls of the gate pocket; and   removing a portion of the recessed gate insulation region located beneath the plurality of fins to define a void between each fin among the plurality of fins and the recessed gate insulation region.   
     
     
         2 . The method of  claim 1 , further comprising extending the recessed gate insulation region below the insulation layer at a predetermined depth. 
     
     
         3 . The method of  claim 2 , further comprising forming a masking layer on an upper surface of the active semiconductor layer, and extending the gate pocket from an upper surface of the masking layer to the recess gate insulation region. 
     
     
         4 . The method of  claim 3 , further comprising arranging the plurality of fins sequentially in the gate pocket. 
     
     
         5 . The method of  claim 4 , further comprising extending the gate insulation layer along a first direction to define a gate length, and forming each fin among the plurality of fins along the first direction to define a fin length not exceeding the gate length. 
     
     
         6 . The method  claim 5 , further comprising forming a gate stack in the gate pocket to cover the plurality of fins. 
     
     
         7 . The method of  claim 1 , further comprising annealing the plurality of fins to form a plurality of nanowires.