Radio transceiver on a chip

Abstract

An entire radio transceiver can be easily integrated into one IC chip. In order to integrate the IF filters on the chip, a heterodyne architecture with a low IF is used. A single, directly modulated VCO is used for both up-conversion during transmission, and down-conversion during reception. Bond-wires are used as resonators in the oscillator tank for the VCO. A TDD scheme is used in the air interface to eliminate cross-talk or leakage. A Gaussian-shaped binary FSK modulation scheme is used to provide a number of other implementation advantages.

1 . A radio transceiver for receiving and transmitting high frequency signals, the radio transceiver comprising:
 a down-conversion section configured to down-convert a received first high frequency signal, generating a down-converted signal;   an up-conversion section configured to up-convert an information signal, to be transmitted, to a second high frequency signal;   a synthesizer, including a variable controlled oscillator;   a low noise amplifier connected to provide the received high-frequency signal to the down-conversion section; and   a filter operatively connected to the down-conversion section for generating a filtered received signal;   wherein the up-conversion section, the down-conversion section, the low-noise amplifier, the filter, and the synthesizer are integrated on a single integrated circuit chip.   
     
     
         2 . The radio transceiver according to  claim 1 , wherein the radio transceiver is adapted to operate according to a time division duplex scheme. 
     
     
         3 . The radio transceiver according to  claim 2 , wherein the variable controlled oscillator is connected to the down-conversion section for down-converting the first high frequency signal during a receive cycle of the time division duplex scheme. 
     
     
         4 . The radio transceiver according to  claim 2 , wherein the variable controlled oscillator is connected to the up-conversion section for up-converting the information signal during a transmit cycle of the time division duplex scheme. 
     
     
         5 . The radio transceiver according to  claim 1 , wherein said filter is a channel selection filter configured to perform channel-selection filtering on the down-converted signal, thereby generating the received filtered signal. 
     
     
         6 . The radio transceiver according to  claim 1 , wherein the radio transceiver is configured to employ a frequency hopping scheme. 
     
     
         7 . The radio transceiver according to  claim 1 , wherein the radio transceiver is configured to employ automatic repeat request error correction. 
     
     
         8 . The radio transceiver according to  claim 1 , further comprising:
 a detector for detecting a received data signal from the filtered received signal, wherein the detector is integrated on the single IC chip.   
     
     
         9 . The radio transceiver according to  claim 1 , wherein the radio transceiver is configured to employ a binary Gaussian-shaped frequency shift keying modulation scheme. 
     
     
         10 . The radio transceiver according to  claim 1 , wherein the radio transceiver is configured to employ continuous variable-slope delta modulation for speech coding. 
     
     
         11 . The radio transceiver according to  claim 1 , wherein the down-conversion section is an image-rejection down-conversion section. 
     
     
         12 . The radio transceiver according to  claim 11 , wherein the image-rejection down-conversion section comprises:
 a first mixer configured to receive the high frequency signal at an input and to foe driven by a local oscillator signal; and   a second mixer configured to receive the high frequency signal at an input and to be driven by a 90-degree phase shifted version of the local oscillator signal.   
     
     
         13 . The radio transceiver according to  claim 12 , wherein the image-rejection down-conversion section further comprises:
 phase-shifting circuitry configured to provide a mutual 90-degree phase shift between output signals from the first and the second mixer; and   a combiner for recombining the 90-degree mutually phase shifted output signals from the first and the second mixer, thereby generating the down-converted signal.   
     
     
         14 . The radio transceiver according to  claim 1 , comprising a power amplifier connected to the up-conversion section:
 wherein the power amplifier is integrated on the single integrated circuit chip.   
     
     
         15 . The radio transceiver according to  claim 1 , wherein the synthesizer comprises a phase-locked loop integrated on the single integrated circuit chip. 
     
     
         16 . The radio transceiver according to  claim 1 , wherein the down-conversion section is configured to down-convert the received first high frequency signal, generating the down-converted signal, in a single frequency-conversion step. 
     
     
         17 . A communications device comprising the radio transceiver according to  claim 1 . 
     
     
         18 . The communication device according to  claim 17 , wherein the communication device is a hand-held communication device.