Semiconductor device

Abstract

There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of rows of through-substrate vias extending in a first direction and having a constant pitch,   wherein each row is staggered with respect to an adjacent row so that a first through-substrate via in a first row is spaced to second and third through-substrate vias in a second row adjacent to the first row by the constant pitch.   
     
     
         2 . The semiconductor device as claimed in  claim 1  wherein the first through-substrate via and the second through-substrate via are connected to a first power supply and the third through-substrate via and a fourth through-substrate via adjacent to the first through-substrate via in the first row are connected to a second power supply. 
     
     
         3 . The semiconductor device as claimed in  claim 2  wherein the first through-substrate via and the second through-substrate via are connected through a first interconnection layer and the third through-substrate via and the fourth through-substrate via are connected through a second interconnection layer. 
     
     
         4 . The semiconductor device as claimed in  claim 3  wherein the first interconnection layer and the second interconnection layer are adjacent layers. 
     
     
         5 . The semiconductor device as claimed in  claim 4  wherein the first interconnection layer is M4 and the second interconnection layer is M5. 
     
     
         6 . The semiconductor device as claimed in  claim 2  wherein the first power supply is a ground voltage. 
     
     
         7 . The semiconductor device as claimed in  claim 2  wherein the first power supply is VSS. 
     
     
         8 . The semiconductor device as claimed in  claim 7  wherein the second power supply is VPERI. 
     
     
         9 . A semiconductor device comprising:
 a plurality of rows of through-substrate vias extending in a first direction and having a constant pitch,   wherein each row is aligned with respect to an adjacent row to form columns of through-substrate vias extending in a second direction orthogonal to the first direction having the constant pitch, and   wherein a first through-substrate via in a first row is connected to a first power supply, a second through-substrate via adjacent the first through-substrate via in the first row is connected to a second power supply, a third through-substrate via in a second row adjacent the first through-substrate is connected to the second power supply, and a fourth through-substrate via in the second row adjacent the second through-substrate via is connected to the first power supply.   
     
     
         10 . The semiconductor device as claimed in  claim 9  wherein the first through-substrate via and the second through-substrate via are connected through a first interconnection layer and the third through-substrate via and the fourth through-substrate via are connected through a second interconnection layer. 
     
     
         11 . The semiconductor device as claimed in  claim 10  wherein the first interconnection layer and the second interconnection layer are adjacent layers. 
     
     
         12 . The semiconductor device as claimed in  claim 11  wherein the first interconnection layer is M4 and the second interconnection layer is M5. 
     
     
         13 . The semiconductor device as claimed in  claim 9  wherein the first power supply is a ground voltage. 
     
     
         14 . The semiconductor device as claimed in  claim 9  wherein the first power supply is VSS. 
     
     
         15 . The semiconductor device as claimed in  claim 14  wherein the second power supply is VPERI.