Semiconductor Device and Method of Forming WLCSP Using Wafer Sections Containing Multiple Die

Abstract

A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections.

What is claimed: 
     
         1 . A semiconductor device, comprising:
 a reconstituted wafer including,
 a plurality of semiconductor die groups disposed in a grid pattern and each including a plurality of semiconductor die attached by an uncut saw street, and 
 an encapsulant deposited between the semiconductor die groups. 
   
     
     
         2 . The semiconductor device of  claim 1 , further including an interconnect structure formed over the encapsulant and semiconductor die groups. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a first semiconductor die group includes a first size semiconductor die and a second semiconductor die group includes a second size semiconductor die different from the first size. 
     
     
         4 . The semiconductor device of  claim 1 , wherein a first semiconductor die group is offset from a second semiconductor die group. 
     
     
         5 . The semiconductor device of  claim 1 , wherein a first semiconductor die group includes at least four semiconductor die. 
     
     
         6 . The semiconductor device of  claim 1 , further including a vertical interconnect structure disposed in the encapsulant. 
     
     
         7 . A semiconductor device, comprising:
 a first semiconductor die group including a plurality of first semiconductor die;   a second semiconductor die group disposed in a peripheral region of the first semiconductor die group and including a plurality of second semiconductor die; and   an encapsulant deposited between the first semiconductor die group and second semiconductor die group.   
     
     
         8 . The semiconductor device of  claim 7 , further including a discrete semiconductor component disposed adjacent to the first semiconductor die group. 
     
     
         9 . The semiconductor device of  claim 7 , further including a third semiconductor die group disposed over the first semiconductor die group and including a plurality of third semiconductor die. 
     
     
         10 . The semiconductor device of  claim 7 , further including an interconnect structure formed over the encapsulant. 
     
     
         11 . The semiconductor device of  claim 7 , wherein the first semiconductor die group is offset from the second semiconductor die group. 
     
     
         12 . The semiconductor device of  claim 7 , wherein the first semiconductor die group and second semiconductor die group are disposed in a grid pattern. 
     
     
         13 . The semiconductor device of  claim 7 , wherein a size of the first semiconductor die differs from a size of the second semiconductor die. 
     
     
         14 . A semiconductor device comprising:
 a reconstituted wafer including,
 a plurality of first semiconductor die attached by a first uncut saw street; and 
 a plurality of second semiconductor die attached by a second uncut saw street and disposed in a peripheral region of the first semiconductor die. 
   
     
     
         15 . The semiconductor device of  claim 14 , further including an encapsulant deposited between the first semiconductor die and second semiconductor die. 
     
     
         16 . The semiconductor device of  claim 14 , further including a first interconnect structure formed over an area between the first semiconductor die and second semiconductor die. 
     
     
         17 . The semiconductor device of  claim 16 , further including a second interconnect structure formed over the area between the first semiconductor die and second semiconductor die opposite the first interconnect structure. 
     
     
         18 . The semiconductor device of  claim 14 , wherein the first semiconductor die are offset from the second semiconductor die. 
     
     
         19 . The semiconductor device of  claim 14 , wherein the first semiconductor die and second semiconductor die are disposed in a grid pattern. 
     
     
         20 . The semiconductor device of  claim 14 , wherein a size of the first semiconductor die differs from a size of the second semiconductor die. 
     
     
         21 . A semiconductor device, comprising:
 a plurality of first semiconductor die attached by an uncut saw street, and   an encapsulant deposited over the first semiconductor die.   
     
     
         22 . The semiconductor device of  claim 21 , further including a second semiconductor die disposed in a peripheral region of the first semiconductor die. 
     
     
         23 . The semiconductor device of  claim 22 , wherein the second semiconductor die is offset from the first semiconductor die. 
     
     
         24 . The semiconductor device of  claim 21 , further including a plurality of second semiconductor die disposed in a grid pattern with the first semiconductor die. 
     
     
         25 . The semiconductor device of  claim 21 , further including an interconnect structure formed over the first semiconductor die.