Floating Body Contact Circuit Method for Improving ESD Performance and Switching Speed

Abstract

Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOT”) and Silicon-On-Sapphire (“SOS”) substrates.

What is claimed is: 
     
         1 . An apparatus for modulating the gate resistance of a transistor having a source, drain, and gate, including a modulated resistor module receiving a modulation signal, including:
 a second resistor having a second resistance, the second resistor configured to be coupled in series between a transistor gate and a gate control terminal for the transistor; and   a bypass module, the bypass module coupled in parallel to the second resistor and configured to controllably bypass the second resistor based on the modulation signal.   
     
     
         2 . The apparatus for modulating the gate resistance of a transistor of  claim 1 , the apparatus further including a first resistor having a first resistance less than the second resistance, wherein the second resistor and the first resistor are configured to be coupled in series between the transistor gate and the gate control terminal. 
     
     
         3 . The apparatus for modulating the gate resistance of a transistor of  claim 1 , the bypass module including a transistor, the bypass module transistor source and drain coupled about the second resistor. 
     
     
         4 . The apparatus for modulating the gate resistance of a transistor of  claim 3 , wherein the bypass module transistor is configured to bypass the second resistor during normal operation. 
     
     
         5 . The apparatus for modulating the gate resistance of a transistor of  claim 3 , wherein the bypass module transistor gate is tied to a signal that exceeds gate thresholds during normal operation. 
     
     
         6 . The apparatus for modulating the gate resistance of a transistor of  claim 3 , wherein the bypass module transistor and the modulated gate resistance transistor are MOSFETs. 
     
     
         7 . The apparatus for modulating the gate resistance of a transistor of  claim 3 , wherein the bypass module transistor and the modulated gate resistance transistor are floating body MOSFETs. 
     
     
         8 . A modulated gate resistance transistor apparatus, including:
 a transistor having a source, drain, and gate; and   a gate resistance module, including:
 a second resistor having a second resistance, the second resistor configured to be coupled in series between the transistor gate and a gate control terminal for the transistor; and 
 a bypass module, the bypass module coupled in parallel to the second resistor and configured to controllably bypass the second resistor based on a modulation signal. 
   
     
     
         9 . The modulated gate resistance transistor apparatus of  claim 8 , the apparatus further including a first resistor having a first resistance, the first resistance less than the second resistance, wherein the second resistor and the first resistor are configured to be coupled in series between the transistor gate and the gate control terminal. 
     
     
         10 . The modulated gate resistance transistor apparatus of  claim 8 , the bypass module including a transistor, the bypass module transistor source and drain coupled about the second resistor. 
     
     
         11 . The modulated gate resistance transistor apparatus of  claim 10 , wherein the bypass module transistor is configured to bypass the second resistor during normal operation. 
     
     
         12 . The modulated gate resistance transistor apparatus of  claim 10 , wherein the bypass module transistor gate is tied to a signal that exceeds gate thresholds during normal operation. 
     
     
         13 . The modulated gate resistance transistor apparatus of  claim 10 , wherein the bypass module transistor and the transistor are MOSFETs. 
     
     
         14 . The modulated gate resistance transistor apparatus of  claim 10 , wherein the bypass module transistor and the transistor are floating body MOSFETs. 
     
     
         15 . The modulated gate resistance transistor apparatus of  claim 9 , wherein the transistor is a four-terminal accumulated charge control floating body MOSFET (ACC MOSFET) device, adapted to control charge accumulated in the body of the ACC MOSFET when the ACC MOSFET is biased to operate in an accumulated charge regime, comprising:
 a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the ACC MOSFET is biased to operate in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer;   an accumulated charge sink (ACS) positioned proximate a distal end of the floating body, wherein the ACS is in electrical communication with the floating body; and   a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS;   
       the apparatus further comprising a third resistor, the third resistor coupled directly or indirectly between the ACS and one of the gate control terminal and the transistor gate terminal, wherein when the ACC MOSFET is operated in the accumulated charge regime, charge accumulated in the body may be removed from the body via the ACS terminal and the third resistor. 
     
     
         16 . The modulated gate resistance transistor apparatus of  claim 15 , wherein the ACC MOSFET has an inherent electro-static discharge (ESD) absorption characteristic and wherein the ESD absorption characteristic of the ACC MOSFET is improved by the addition of the third resistor in the apparatus. 
     
     
         17 . The modulated gate resistance transistor apparatus of  claim 15 , wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology. 
     
     
         18 . The modulated gate resistance transistor apparatus of  claim 15 , wherein the third resistor is coupled directly or indirectly between the ACS and the gate control terminal. 
     
     
         19 . The modulated gate resistance transistor apparatus of  claim 18 , wherein the third resistor is coupled indirectly between the ACS and the gate control terminal. 
     
     
         20 . The modulated gate resistance transistor apparatus of  claim 19 , wherein a diode is coupled in series with the third resistor. 
     
     
         21 . The modulated gate resistance transistor apparatus of  claim 15 , wherein a diode is coupled in series with the third resistor. 
     
     
         22 . The modulated gate resistance transistor apparatus of  claim 15 , wherein the third resistor has a resistance from about 100 kilo ohms to several Mega ohms. 
     
     
         23 . An accumulated charge regime apparatus, the apparatus including:
 a four-terminal accumulated charge control floating body MOSFET (ACC MOSFET) device, adapted to control charge accumulated in the body of the MOSFET when the MOSFET is biased to operate in an accumulated charge regime, comprising:
 a gate, drain, source, floating body, and a gate oxide layer positioned between the gate and the floating body, wherein the ACC MOSFET is biased to operate in the accumulated charge regime when the MOSFET is biased to operate in an off-state (non-conducting state) and charge accumulates within the body in a region proximate and underneath the gate oxide layer; 
 an accumulated charge sink (ACS) positioned proximate a distal end of the floating body, wherein the ACS is in electrical communication with the floating body; and 
 a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS; 
   a gate control terminal;   a first resistor, the first resistor coupled between the gate control terminal and to the gate terminal; and   a second resistor, the second resistor coupled directly or indirectly between the ACS and one of the gate control terminal and the transistor gate terminal,   wherein, when the MOSFET is operated in the accumulated charge regime, charge accumulated in the body may be removed from the body via the ACS terminal and the second resistor.   
     
     
         24 . The accumulated charge regime apparatus of  claim 23 , wherein the ACC MOSFET has an inherent electro-static discharge (ESD) absorption characteristic and wherein the ESD absorption characteristic of the ACC MOSFET is improved by the addition of the second resistor in the apparatus. 
     
     
         25 . The ACC MOSFET of  claim 23 , wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology. 
     
     
         26 . The ACC MOSFET of  claim 23 , wherein the second resistor is coupled directly or indirectly between the ACS and the gate control terminal. 
     
     
         27 . The ACC MOSFET of  claim 26 , wherein the second resistor is coupled indirectly between the ACS and the gate control terminal. 
     
     
         28 . The ACC MOSFET of  claim 23 , wherein a diode is coupled in series with the second resistor. 
     
     
         29 . The ACC MOSFET of  claim 23 , wherein a diode is coupled between the second resistor and the ACS. 
     
     
         30 . The ACC MOSFET of  claim 27 , wherein a diode is coupled in series with the second resistor. 
     
     
         31 . The ACC MOSFET of  claim 27 , wherein a diode is coupled between the second resistor and the ACS. 
     
     
         32 . The ACC MOSFET of  claim 23 , wherein the second resistor has a resistance from about 100 kilo ohms to several Mega ohms.