Software-based thread remapping for power savings

Abstract

On a multi-core processor that supports simultaneous multi-threading, the power state for each logical processor is tracked. Upon indication that a logical processor is ready to transition into a deep low power state, software remapping (e.g., thread-hopping) may be performed. Accordingly, if multiple logical processors, on different cores, are in a low-power state, they are re-mapped to same core and the core is then placed into a low power state. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A method comprising:
 based on power state information for a first logical processor of a first core and a first logical processor of a second core, swapping work from the first logical processor of the first core to the first logical processor of the second core;   placing the first logical processor of the first core into a power-off state;   and   placing the first core into a power-off state.   
     
     
         2 . The method of  claim 1 , wherein the swapping is performed by control software of a computing platform that includes the first and second cores. 
     
     
         3 . The method of  claim 2 , wherein the swapping is performed by an operating system of the computing platform. 
     
     
         4 . The method of  claim 2 , wherein the swapping includes performing a software-based context switch. 
     
     
         5 . The method of  claim 1 , wherein the first and second cores reside in a same die package. 
     
     
         6 . The method of  claim 1 , wherein the swapping includes remapping a thread identifier associated with the second core to the first core. 
     
     
         7 . A system comprising:
 a chip package that includes a first core with a first logical processor and a second core with a second logical processor;   a scheduler module coupled with the chip package, the scheduler module to swap, based on power state information related to the first logical processor and the second logical processor, work from the first logical processor to the second logical processor; and   a power module coupled with the scheduler module, the power module to place the first logical processor into a power-off state, and place the first core into a power-off state.   
     
     
         8 . The system of  claim 7 , wherein the power module is further to place the first logical processor in the power-off state subsequent to the swap. 
     
     
         9 . The system of  claim 7 , wherein the power module is further to place the first core into the power-off state subsequent to placement of the first logical processor into the power-off state. 
     
     
         10 . The system of  claim 7 , wherein said scheduler module and said power module are software modules. 
     
     
         11 . The system of  claim 7 , wherein the first core and the second core reside on a same die package. 
     
     
         12 . The system of  claim 7 , wherein the first core and the second core are members of a processing element having an integrated memory controller. 
     
     
         13 . One or more non-transitory computer-readable media comprising instructions to cause an element of a computing platform, upon execution of the instructions by one or more processors associated with the element, to:
 based on power state information for a first logical processor of a first core and a first logical processor of a second core, swap work from the first logical processor of the first core to the first logical processor of the second core;   place the first logical processor of the first core into a power-off state; and   place the first core into a power-off state.   
     
     
         14 . The one or more non-transitory computer-readable media of  claim 13 , wherein the element of the computing platform is control software of the computing platform. 
     
     
         15 . The one or more non-transitory computer-readable media of  claim 14 , wherein the element of the computing platform is an operating system of the computing platform. 
     
     
         16 . The method of  claim 14 , wherein the instructions to swap include instructions to perform a software-based context switch. 
     
     
         17 . The method of  claim 13 , wherein the first and second cores reside in a same die package. 
     
     
         18 . The method of  claim 13 , wherein the instructions to swap includes instructions to remap a thread identifier associated with the second core to the first core. 
     
     
         19 . A computing platform comprising:
 based on power state information for a first logical processor of a first core and a first logical processor of a second core, means to swapping work from the first logical processor of the first core to the first logical processor of the second core;   means to place the first logical processor of the first core into a power-off state; and   means to place the first core into a power-off state.   
     
     
         20 . The computing platform of  claim 19 , wherein the means to swap include control software of a computing platform that includes the first and second cores. 
     
     
         21 . The computing platform of  claim 20 , wherein the means to swap include an operating system of the computing platform. 
     
     
         22 . The computing platform of  claim 20 , wherein the means to swap include means to perform a software-based context switch. 
     
     
         23 . The computing platform of  claim 19 , wherein the first and second cores reside in a same die package. 
     
     
         24 . The computing platform of  claim 19 , wherein the means to swap include means to remap a thread identifier associated with the second core to the first core.