Speeding up defect diagnosis techniques

Abstract

Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit.

1 - 15 . (canceled) 
     
     
         16 . A method of generating a fault dictionary for use in diagnosing faults in an electronic circuit, the method comprising:
 for a selected fault,
 simulating one or more test patterns being applied to the electronic circuit in the presence of the selected fault; 
 determining test responses to the one or more test patterns that indicate the presence of the selected fault using the simulation; and 
 storing, in one or more computer-readable media, a fault dictionary entry that identifies the selected fault and identifies the test responses that indicate the presence of the selected fault. 
   
     
     
         17 . The method of  claim 16 , wherein the fault dictionary entry is the only entry in the dictionary for the selected fault. 
     
     
         18 . The method of  claim 16 , wherein the fault dictionary entry does not indicate which of the one or more test patterns caused the test responses that indicate the presence of the selected fault to be produced. 
     
     
         19 . The method of  claim 16 , further comprising repeating the acts of simulating, determining, and storing for multiple additional faults. 
     
     
         20 . The method of  claim 16 , wherein the act of determining the test responses comprises generating x-bit signatures from full test responses of the electronic circuit to the one or more test patterns. 
     
     
         21 . The method of  claim 20 , wherein the act of storing the fault dictionary entry comprises storing the corresponding x-bit signatures as the test responses that indicate the presence of the selected fault. 
     
     
         22 . The method of  claim 21 , wherein the x-bit signatures are generated by a simulated multiple-input signature register (MISR). 
     
     
         23 . The method of  claim 16 , further comprising storing information indicative of which clocks clocked scan cells that captured failing bits indicative of the presence of the selected fault during the simulation. 
     
     
         24 . One or more non-transitory computer-readable media storing instructions configured to cause a computer to perform a method, the method comprising:
 for a selected fault,
 simulating one or more test patterns being applied to the electronic circuit in the presence of the selected fault; 
 determining test responses to the one or more test patterns that indicate the presence of the selected fault using the simulation; and 
 storing a fault dictionary entry that identifies the selected fault and identifies the test responses that indicate the presence of the selected fault. 
   
     
     
         25 - 44 . (canceled) 
     
     
         45 . The one or more computer-readable media of  claim 24 , wherein the fault dictionary entry is the only entry in the dictionary for the selected fault. 
     
     
         46 . The one or more computer-readable media of  claim 24 , wherein the fault dictionary entry does not indicate which of the one or more test patterns caused the test responses that indicate the presence of the selected fault to be produced. 
     
     
         47 . The one or more computer-readable media of  claim 24 , further comprising repeating the acts of simulating, determining, and storing for multiple additional faults. 
     
     
         48 . The one or more computer-readable media of  claim 24 , wherein the act of determining the test responses comprises generating x-bit signatures from full test responses of the electronic circuit to the one or more test patterns. 
     
     
         49 . The one or more computer-readable media of  claim 48 , wherein the act of storing the fault dictionary entry comprises storing the corresponding x-bit signatures as the test responses that indicate the presence of the selected fault. 
     
     
         50 . The one or more computer-readable media of  claim 49 , wherein the x-bit signatures are generated by a simulated multiple-input signature register (MISR). 
     
     
         51 . The one or more computer-readable media of  claim 24 , further comprising storing information indicative of which clocks clocked scan cells that captured failing bits indicative of the presence of the selected fault during the simulation.