III-Nitride Semiconductor Device Fabrication

Abstract

A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.

1 - 31 . (canceled) 
     
     
         32 . A method for fabricating a III-nitride semiconductor device, said method comprising:
 forming a field insulation layer on a III-nitride multi-layer body, said III-nitride multi-layer body including an active III-nitride heterojunction;   removing selected portions of said field insulation layer to provide openings over said active III-nitride heterojunction;   forming a gate insulation body thinner than said field insulation body at a bottom of said openings;   removing a portion of at least one of said gate insulation bodies from said bottom of at least one of said openings to expose said active III-nitride heterojunction;   forming a power electrode in said at least one of said openings.   
     
     
         33 . The method of  claim 32 , further comprising forming a barrier body over said gate dielectric body after forming said gate insulation bodies. 
     
     
         34 . The method of  claim 33 , wherein said barrier body is formed by depositing a barrier metal. 
     
     
         35 . The method of  claim 34 , wherein said barrier metal prevents damage to said gate dielectric during a rapid thermal anneal. 
     
     
         36 . The method of  claim 34 , wherein said barrier metal comprises TiN. 
     
     
         37 - 46 . (canceled) 
     
     
         47 . The method of  claim 34 , wherein said barrier metal comprises at least one metal selected from the group consisting of Ta, W, Si, Mo, Cr, Co, and Pd. 
     
     
         48 . The method of  claim 34 , wherein said barrier metal comprises at least one alloy selected from the group consisting of TiSiN, TaN, TaSiN, WN, WSiN, and WBN. 
     
     
         49 . A method for fabricating a III-nitride semiconductor device, said method comprising:
 forming a field insulation layer on a III-nitride multi-layer body, said III-nitride multi-layer body including an active III-nitride heterojunction;   removing selected portions of said field insulation layer to provide openings over said active III-nitride heterojunction;   forming a gate insulation body at a bottom of said openings;   removing a portion of at least one of said gate insulation bodies from said bottom of at least one of said openings to expose said active III-nitride heterojunction;   forming a power electrode in said at least one of said openings.   
     
     
         50 . The method of  claim 49 , further comprising forming a barrier body over said gate dielectric body. 
     
     
         51 . The method of  claim 50 , wherein said barrier body is formed by depositing a barrier metal. 
     
     
         52 . The method of  claim 51 , wherein said barrier metal prevents damage to said gate dielectric during a rapid thermal anneal. 
     
     
         53 . The method of  claim 51 , wherein said barrier metal comprises TiN. 
     
     
         54 . The method of  claim 51 , wherein said barrier metal comprises at least one metal selected from the group consisting of Ta, W, Si, Mo, Cr, Co, and Pd. 
     
     
         55 . The method of  claim 51 , wherein said barrier metal comprises at least one alloy selected from the group consisting of TiSiN, TaN, TaSiN, WN, WSiN, and WBN.