Multi-time programmable device

Abstract

Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.

What is claimed is: 
     
         1 - 9 . (canceled) 
     
     
         10 . A method of forming a device comprising:
 providing a substrate comprising a device region prepared with first and second isolation regions surrounding the device region;   forming a multi-time programmable (MTP) memory cell having a single transistor formed on the device region, wherein forming the MTP memory cell comprises
 forming a gate having first and second sidewalls disposed over a channel region in the substrate, the channel region comprises first and second sub-regions, the gate includes a gate electrode and gate dielectric comprising a programmable resistive layer disposed between the gate electrode and substrate, and the gate partially overlaps the second isolation region adjacent to the second sidewall of the gate; and 
 forming a heavily doped region of a first polarity type in the substrate in between the first isolation region and the first sidewall of the gate, 
 wherein the gate dielectric above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive layer above the other first or second sub-region. 
   
     
     
         11 . The method of  claim 10  wherein forming the gate comprises:
 forming a dielectric layer over the device region; 
 patterning the dielectric layer by removing a portion of the dielectric layer over the second sub-region; 
 forming the programmable resistive layer and gate electrode layer over the device region, wherein the programmable resistive layer covers the patterned dielectric layer; and 
 patterning the dielectric, programmable resistive and gate electrode layers, wherein the patterned dielectric layer remains over the first sub-region while the patterned programmable resistive and gate electrode layers remain over the first and second sub-regions. 
 
     
     
         12 . The method of  claim 11  wherein:
 the programmable resistive layer comprises NiO 2 , HfO 2 , ZrO 2 , AlO 2 , TiO 2 , Ta 2 O 5 , WOx, TiON, GeO, SiO 2  or SnO 2 ; 
 the gate electrode comprises polysilicon, Ru, W, Pt, TiN, Ti, Zr, TaN, Si or Al; and 
 the dielectric comprises a high k dielectric material. 
 
     
     
         13 . The method in  claim 10  comprising forming first and second type sidewall spacers on the first and second sidewalls of the gate. 
     
     
         14 . The method of  claim 10  comprising:
 forming a buffer layer over the device region; 
 patterning the buffer layer to form a first patterned buffer layer by removing a portion of the buffer layer; 
 forming the programmable resistive and the gate electrode layers over the device region, wherein the programmable resistive layer covers the first patterned buffer layer; and 
 patterning the buffer, programmable resistive and gate electrode layers, wherein a second patterned buffer layer remains over the second sub-region while the patterned programmable resistive and gate electrode layers remain over the first and second sub-regions. 
 
     
     
         15 . The method of  claim 10  wherein forming the gate comprises:
 forming the programmable resistive and a gate electrode layers over the device region; and 
 patterning the programmable resistive and gate electrode layers, wherein the patterned resistive and gate electrode layers remain over the first and second sub-regions. 
 
     
     
         16 . The method of  claim 15  further comprising implanting metallic dopants into the portion of the resistive layer over the second sub-region. 
     
     
         17 . The method of  claim 10  comprising:
 forming a dielectric layer and a dummy layer on the dielectric layer over the device region; 
 patterning the dielectric and dummy layers, wherein the patterned dielectric and dummy layers remain over the first and second sub-regions form a dummy gate; 
 forming first and second type sidewall spacers on first and second sidewalls of the dummy gate; and 
 forming an ILD layer over the substrate, wherein top surfaces of the ILD, sidewall spacers and dummy gate are about coplanar with each other. 
 
     
     
         18 . The method of  claim 17  wherein forming the gate comprises:
 removing the dummy layer and a portion of the patterned dielectric layer over the second sub-region so that a portion of the dielectric layer remains on the first sub-region; and 
 forming the programmable resistive layer and gate electrode layer over the device region, wherein the resistive layer covers the patterned dielectric layer over the first sub-region. 
 
     
     
         19 . The method in  claim 17  further comprising:
 forming a buffer layer over the device region; and 
 patterning the buffer layer, wherein the patterned buffer layer remains over the second sub-region and the patterned buffer layer, dielectric and dummy layers form the dummy gate. 
 
     
     
         20 . The method of  claim 19  wherein forming the gate comprises:
 removing the patterned dielectric and dummy layers over the first and second sub-regions so that the patterned buffer layer over the second sub-region is exposed; and 
 forming the programmable resistive layer and gate electrode layer over the device region, wherein the programmable resistive layer covers the buffer layer over the second sub-region. 
 
     
     
         21 . The method of  claim 17  wherein forming the gate comprises:
 removing the dummy layer and the patterned dielectric over the first and second sub-regions to expose a portion of a top surface of the substrate; 
 forming the programmable resistive layer over the device region, wherein the programmable resistive layer lines a top surface of the ILD and the exposed portion of the substrate; and 
 implanting metallic dopants into the portion of the programmable resistive layer over the second sub-region. 
 
     
     
         22 . The method of  claim 21  wherein the metallic dopants change characteristic of the programmable resistive layer such that filaments or conduction paths are easily formed. 
     
     
         23 . The method of  claim 21  wherein the metallic dopants are implanted at a tilt angle with respect to a plane perpendicular to a surface of the substrate. 
     
     
         24 . The method of  claim 10  comprising:
 forming a buffer layer over the second sub-region and directly contacts the substrate, wherein the portion of the programmable resistive layer above the second sub-region and directly contacts the buffer layer is more susceptible for programming relative to the portion of the programmable resistive layer above the first sub-region which directly contacts the substrate. 
 
     
     
         25 . The method of  claim 24  wherein the buffer layer comprises materials which change characteristic of the programmable resistive layer thereover such that filaments or conduction paths are easily formed. 
     
     
         26 . The method of  claim 10  wherein the portion of the programmable resistive layer over the second sub-region comprises dopants which change the characteristic of the programmable resistive layer such that filaments or conduction paths are easily formed. 
     
     
         27 . The method of  claim 11  wherein the patterned dielectric layer is disposed over the first sub-region and directly contacts the substrate, and wherein the portion of the programmable resistive layer above the second sub-region directly contacts the substrate and is more susceptible for programming relative to the portion of the programmable resistive layer above the patterned dielectric layer. 
     
     
         28 . The method of  claim 27  wherein the portion of the programmable resistive layer above the second sub-region generates a number of filaments or conduction paths when an appropriate voltage is applied. 
     
     
         29 . The method of  claim 10  wherein:
 the heavily doped region formed adjacent to the first sub-region and defines an access portion of the memory cell; and 
 the second isolation region formed adjacent to the second sidewall of the gate and the second sub-region, the second isolation region partially underlaps the gate and defines a programmable portion of the memory cell. 
 
     
     
         30 . The method of  claim 10  wherein forming the gate comprises forming a dielectric layer over the first sub-region and directly contacts the substrate, and wherein the portion of the programmable resistive layer above the second sub-region directly contacts the substrate and is more susceptible for programming relative to the portion of the programmable resistive layer above the dielectric layer.