Semiconductor device and interconnect substrate

Abstract

A semiconductor device includes a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon. The interconnect substrate includes a first main surface formed with a plurality of electrodes connected electrically to the semiconductor chip, a second main surface opposing the first main surface, and an interconnect region interposed between the first main surface and the second main surface. The electrodes include a plurality of first electrodes and second electrodes arranged orderly for receiving supply of signals. The first electrodes for signal and the second electrodes are disposed being dispersed in the arrangement thereof, and the interconnect region includes a core substrate, a plurality of interconnect layers formed on both surfaces of the core substrate respectively.

What is claimed is: 
     
         1 . A semiconductor device comprising a semiconductor chip and an interconnect substrate having the semiconductor chip mounted thereon,
 wherein the interconnect substrate comprises:   a first main surface formed with a plurality of electrodes connected electrically to the semiconductor chip;   a second main surface opposing the first main surface; and   an interconnect region interposed between the first main surface and the second main surface,   wherein the electrodes include a plurality of first electrodes and second electrodes arranged orderly for receiving supply of signals, and   wherein the first electrodes for signal and the second electrodes are disposed being dispersed in the arrangement thereof, and   wherein the interconnect region includes:   a core substrate;   a plurality of interconnect layers formed on both surfaces of the core substrate respectively;   a plurality of first through holes that pass through the core substrate;   a plurality of first vias that pass through the interconnect layer formed to the core substrate on the side of the first main surface;   a plurality of first interconnects electrically connected with the first electrodes; and   a plurality of second interconnects electrically connected to with the second electrodes,   wherein each first through hole is connected to the first interconnect at a position spaced apart from the first electrode by a first interconnect length, and   wherein the first via is connected to the second interconnect at a position spaced apart from the second electrode by a second interconnect length that is substantially equal with the first interconnect length.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the interconnect region further includes:   a plurality of second through holes passing through the core substrate; and   a plurality of second vias passing through the interconnect layer formed to the core substrate on the side of the second main surface,   wherein each second through hole is connected with the second interconnect at a position spaced apart from the second electrode by a third interconnect length longer than the first interconnect length, and   wherein each second via is connected with the first interconnect at a position spaced apart from the first electrode by a fourth interconnect length that is substantially equal with the third interconnect length.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein
 the first through hole and the first via do not overlap in a plan view.   
     
     
         4 . The semiconductor device according to  claim 2 , wherein
 the first interconnect comprises a first differential interconnect pair formed by two interconnects in parallel and the second signal interconnect comprises a second differential interconnect pair formed by two interconnects in parallel.   
     
     
         5 . The semiconductor device according to  claim 2 , wherein
 one of the first electrode and the second electrode comprises a receiving electrode for inputting a signal to the semiconductor chip and an other of the first electrode and the second electrode comprises a transmitting electrode for outputting a signal from the semiconductor chip.   
     
     
         6 . The semiconductor device according to  claim 2 , wherein
 the diameter of the uppermost land and the diameter of the lowermost land connected to the first through hole are different in a cross sectional view.   
     
     
         7 . The semiconductor device according to  claim 2 , wherein
 the first through hole is connected with a plurality of lands in a vertical direction in a cross sectional view.   
     
     
         8 . The semiconductor device according to  claim 2 , wherein
 the diameter of the uppermost land and the diameter of the lowermost land connected to the first via are different in a cross sectional view.   
     
     
         9 . The semiconductor device according to  claim 2 , wherein
 a plurality of lands are connected in a vertical direction to the first via in a cross sectional view.   
     
     
         10 . The semiconductor device according to  claim 2 , wherein
 a portion of a plurality of the first vias is connected by way of one land to the second interconnect and a remaining portion of the plurality of the first vias is connected to the second interconnect by way of a plurality of lands.   
     
     
         11 . The semiconductor device according to  claim 2 , wherein
 the diameter of the land for the first via is larger than that for the second via.   
     
     
         12 . The semiconductor device according to  claim 2 , wherein
 the first via has a larger land diameter than that of the adjacent via for connecting adjacent interconnect layers to each other.   
     
     
         13 . The semiconductor device according to  claim 2 , wherein the semiconductor chip has a plurality of interface buffers connected being corresponded respectively to the first signal terminal and the second signal terminal.