Non-volatile memory device integrated with cmos soi fet on a single chip

Abstract

A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor on insulator (SOI) field effect transistor (FET) formed in a predefined SOI device region of an SOI substrate, the SOI FET comprising: a first portion of a buried oxide (BOX) layer, a first portion of an SOI layer, a gate dielectric layer overlying the first portion of the SOI layer, and a gate conductor layer overlying the gate dielectric; and   a nonvolatile memory device formed in a predefined nonvolatile semiconductor memory device region of the SOI substrate, the nonvolatile memory device comprising: a tunnel oxide layer overlying a semiconductor substrate, a floating gate layer overlying the tunnel oxide layer, a blocking oxide layer overlying the floating gate layer and a control gate layer overlying the blocking oxide layer, the tunnel oxide layer comprises a second portion of the BOX layer coplanar with the first portion of the BOX layer in the SOI device region and the floating gate layer comprises a second portion of the SOI layer coplanar with the first portion of the SOI layer in the SOI device region.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the blocking oxide layer coplanar with the gate dielectric layer in the SOI device region. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein a material of the blocking oxide layer is substantially different from a material of the gate dielectric layer. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the control gate layer coplanar with the gate conductor layer in the SOI device region. 
     
     
         5 . The semiconductor structure of  claim 1 , further comprising at least one contact trench formed in a substrate contact region of the SOI substrate, the substrate contact region adjacent to the nonvolatile semiconductor memory device region, the at least one contact trench including a contact that is electrically connected to the semiconductor substrate. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the SOI FET is an n-type field effect transistor (NFET) or a p-type field effect transistor (PFET). 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising a first pair of sidewall spacers formed on sidewalls of the SOI FET and a second pair of sidewall spacers formed on sidewalls of the nonvolatile memory device. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the BOX layer has a thickness of approximately 3 nm to approximately 20 nm. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the SOI layer has a thickness of approximately 3 nm to approximately 10 nm. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein the blocking oxide layer and the gate dielectric layer comprise a multi-layer dielectric material.