Rotated channel field effect transistor

Abstract

A transistor device, such as a rotated channel metal oxide/insulator field effect transistor (RC-MO(I)SFET), includes a substrate including a non-polar or semi-polar wide band gap substrate material such as an Al 2 O 3 or a ZnO or a Group-III Nitride-based material, and a first structure disposed on a first side of the substrate comprising of AlInGaN-based and/or ZnMgO based semiconducting materials. The first structure further includes an intentional current-conducting sidewall channel or facet whereupon additional semiconductor layers, dielectric layers and electrode layers are disposed and upon which the field effect of the dielectric and electrode layers occurs thus allowing for a high density monolithic integration of a multiplicity of discrete devices on a common substrate thereby enabling a higher power density than in conventional lateral power MOSFET devices.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a buffering layer disposed above the substrate;   a channel layer having a first portion and a second portion, wherein the first portion has a first thickness and the second portion has a second thickness, and wherein a wall adjoining the first portion and the second portion includes a sidewall channel; and   a plurality of electrodes configured to be in electrical communication with the sidewall channel, wherein the plurality of electrodes is configured to receive voltages to provide a controlled current flow through the semiconductor device.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the channel layer includes one or more of Zn x Mg 1-x O, Al x Ga 1-x N, and Al y In z Ga 1-y-z N, wherein 0≦x≦1, 0≦y≦0.5, 0≦z≦0.5. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the substrate includes a non-polar or semi-polar semiconductor material. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the non-polar material or semi-polar semiconductor material includes Al 2 O 3 , ZnO, or a Group-III Nitride. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the sidewall channel is configured to accommodate a two dimensional electron gas formed by a piezo polarization of the channel layer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the sidewall channel is substantially perpendicular to the first portion and the second portion of the channel layer. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the sidewall channel is configured to substantially avoid crystalline defects of the channel layer. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the crystalline defects of the channel layer include threading dislocations, and misfit and prismatic dislocations. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the buffering layer includes Zn x Mg 1-x O, wherein 0≦x<1, 0≦y<0.5, 0≦z<0.5. 
     
     
         10 . The semiconductor device of  claim 1 , further comprising an insulating layer disposed between the channel layer and one of the plurality of electrodes. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the channel layer includes a third portion having a third thickness, wherein a second wall adjoining the second portion and the third portion includes a second sidewall channel. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the first thickness and the third thickness are substantially identical. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the first thickness and the third thickness are different. 
     
     
         14 . An integrated device comprising:
 a substrate;   a buffering layer disposed above the substrate; and   a plurality of depletion mode devices, wherein at least one of the plurality of depletion mode device comprises:
 a channel layer having a first portion and a second portion, wherein the first portion has a first thickness and the second portion has a second thickness, and wherein a wall adjoining the first portion and the second portion includes a sidewall channel; and 
 a plurality of electrodes configured to be in electrical communication with the sidewall channel, wherein the plurality of electrodes is configured to receive voltages to provide a controlled current flow through the depletion mode device; 
   wherein one of the plurality of electrodes in one of the plurality of depletion mode devices is configured to be in electrical communication with one of the plurality of electrodes in another depletion mode device.   
     
     
         15 . An integrated device comprising:
 a substrate;   a buffering layer disposed above the substrate; and   at least one enhancement mode device, wherein the at least one enhancement mode device comprises:
 a channel layer having a third portion and a fourth portion, wherein a wall adjoining the third portion and the fourth portion includes a sidewall channel; 
 a plurality of electrodes configured to be in electrical communication with the sidewall channel, wherein the plurality of electrodes is configured to receive voltages to provide a controlled current flow through the enhancement mode device; and 
 an insulating layer disposed between the channel layer and one of the plurality of electrodes; 
   wherein one of the plurality of electrodes in one of the at least one enhancement mode device is configured to be in electrical communication with one of the plurality of electrodes in another one of the at least one enhancement mode device.   
     
     
         16 . The integrated device of  claim 15 , further comprising:
 a plurality of depletion mode devices, wherein at least one of the plurality of depletion mode device comprises:
 a channel layer having a first portion and a second portion, wherein the first portion has a first thickness and the second portion has a second thickness, and wherein a wall adjoining the first portion and the second portion includes a sidewall channel; and 
 a plurality of electrodes configured to be in electrical communication with the sidewall channel, wherein the plurality of electrodes is configured to receive voltages to provide a controlled current flow through the depletion mode device; 
   wherein one of the plurality of electrodes in one of the plurality of depletion mode devices is configured to be in electrical communication with one of the plurality of electrodes in one of the at least one enhancement mode device.   
     
     
         17 . The integrated device of  claim 16 , further comprising a spacer disposed between one of the plurality of depletion mode devices and one of the at least one enhancement mode device, wherein the spacer includes an insulating material to electrically isolate the channel layer of the one of depletion mode devices and the channel layer of one of the at least one enhancement mode device. 
     
     
         18 . The integrated device of  claim 17 , wherein the electrodes of one of the plurality of depletion mode devices includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the electrodes of one of the at least one enhancement mode device includes a second gate electrode, a second source electrode, and a second drain electrode, and wherein the first source electrode is coupled to a power supply, the first gate electrode and the first drain electrode are coupled to the second drain electrode, and the second source electrode is coupled to a ground potential. 
     
     
         19 . The integrated device of  claim 16 , wherein the channel layer of one of the plurality of the depletion mode device and the channel layer of one of the at least one enhancement mode device comprise a single semiconducting layer. 
     
     
         20 . The integrated device of  claim 16 , wherein the substrate includes a non-polar or semi-polar semiconductor material.