Fin-type memory

Abstract

Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

What is claimed is: 
     
         1 . A device comprising:
 a substrate prepared with a lower electrode level with at least one bottom electrode;   fin stacks disposed on and contacts the bottom electrodes at the lower electrode level;   an interlevel dielectric (ILD) layer disposed on the substrate, the ILD layer fills spaces around the fin stacks; and   an upper electrode level disposed on the ILD layer, the upper electrode level having at least one top electrode in contact with the fin stacks, the electrodes and fin stacks form fin-type memory cells, wherein
 the fin stacks comprise at least one secondary fin body and at least one main fin body disposed over and contacts the at least one secondary fin body, and 
 the at least one secondary fin body contacts the at least one bottom electrode while the at least one main fin body contacts the at least one top electrode. 
   
     
     
         2 . The device of  claim 1  wherein the at least one main fin body is coupled to its respective secondary fin body. 
     
     
         3 . The device of  claim 2  comprising dielectric liners lining sides of the fin stacks and top surface of the lower electrode level. 
     
     
         4 . The device of  claim 2  comprising an interfin dielectric (IFD) layer, wherein the IFD layer fills the space between adjacent fin stacks. 
     
     
         5 . The device of  claim 4  wherein the IFD layer and the dielectric liners comprise the same material. 
     
     
         6 . The device of  claim 4  wherein the IFD layer comprises low k dielectric, porous dielectric or air. 
     
     
         7 . The device of  claim 4  wherein the IFD and the ILD layers comprise the same material. 
     
     
         8 . The device of  claim 4  wherein the dielectric liners, the IFD and ILD layers comprise top surfaces which are coplanar with each other. 
     
     
         9 . The device of  claim 1  wherein the fin stacks comprise at least first and second adjacent main fin bodies, wherein the adjacent main fin bodies share a common secondary fin body. 
     
     
         10 . The device of  claim 9  comprising dielectric liners lining sides of the fin stacks and top surface of the lower electrode level. 
     
     
         11 . The device of  claim 10  comprising an interfin dielectric (IFD) layer, wherein the IFD layer fills the space between adjacent fin stacks. 
     
     
         12 . The device of  claim 1  wherein the main fin body is a resistive element having multiple stable resistive states. 
     
     
         13 . The device of  claim 1  wherein the fin stacks comprise fin stacks of a phase change random access memory (PCRAM) or a resistive random access memory (RRAM). 
     
     
         14 . The device of  claim 13  wherein:
 the main fin body of the PCRAM comprises a phase change (PC) material which comprises chalcogenide material and the secondary fin body of the PCRAM comprises a heat generating (HG) material which comprises titanium nitride. 
 
     
     
         15 . The device of  claim 13  wherein:
 the main fin body of the RRAM comprises a programmable resistive (PR) material which comprises hafnium oxide or tantalum oxide; and 
 the secondary fin body of the RRAM comprises a PR material, an electrode material or an oxygen gettering material. 
 
     
     
         16 . The device of  claim 15  wherein the electrode material comprises titanium, TiN or TaN. 
     
     
         17 . The device of  claim 15  wherein the oxygen gettering material comprises hafnium, aluminum oxide or aluminum hafnium oxide. 
     
     
         18 . The device of  claim 1  wherein the at least one top or the bottom electrode is connected to wordlines while the other electrodes are connected to bitlines. 
     
     
         19 . The device of  claim 2  wherein the top and bottom electrodes are indirectly connected to wordlines or bitlines via selection elements, wherein the selection elements comprise transistors or self-rectifying diodes or contacts. 
     
     
         20 . The device of  claim 1  wherein the top and bottom electrodes are directly connected to wordlines or bitlines to form a cross-point memory array.