US2015118801A1PendingUtilityA1
Semiconductor device
Est. expiryMay 11, 2032(~5.8 yrs left)· nominal 20-yr term from priority
H10W 74/15H10W 90/734H10W 90/724H10W 72/07236H10W 72/252H10W 72/248H10W 72/222H10W 72/00H10W 40/228H10W 74/012H10W 74/01H10W 70/635H10W 70/65H10W 90/701H01L 2924/14H01L 24/81H01L 2224/13147H01L 21/56H01L 2924/15311H01L 2224/81801H01L 2224/16227
45
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Claims
Abstract
To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of manufacturing a semiconductor device comprising:
(a) preparing a semiconductor chip having a main surface over which a plurality of protruding electrodes and a wiring board having a first main surface over which a plurality of terminals are formed and a second main surface over which a plurality of lands are formed opposite the first main surface; (b) disposing a sealing resin over the first main surface of the wiring board; and (c) after the step (b), mounting the semiconductor chip over the first main surface of the wiring board via the sealing resin such that the main surface of the semiconductor chip faces to the first main surface of the wiring board and electrically connecting the protruding electrodes of the semiconductor chip to the terminals of the wiring board, respectively, wherein the wiring board comprises: (a1) an insulating film formed over the second main surface; (a2) among the terminals, a plurality of first terminals and a plurality of second terminals placed in a first area of the wiring board; (a3) a plurality of first through-holes placed in a second area inside the first area and electrically coupled to the first terminals, respectively; (a4) among the lands, a plurality of first lands electrically coupled to the first through-holes, respectively, and placed so as to overlap with the second area in plan view; (a5) a plurality of second through-holes placed in a third area outside the first area and electrically coupled to the second terminals, respectively; and (a6) among the lands, a plurality of second lands electrically coupled to the second through-holes, respectively, and placed so as to overlap with the third area in plan view, wherein the insulating film has therein a plurality of openings, wherein the first lands are placed so as to overlap with the semiconductor chip in plan view, and wherein the first lands are embraced in the openings, respectively.
2 . The method according to claim 1 , wherein, in the step (c), the sealing resin is cured between the main surface of the semiconductor chip and the first surface of the wiring board by heating.
3 . The method according to claim 2 , wherein, in the step (c), each of the protruding electrodes of the semiconductor chip are electrically connected to each of the terminals of the wiring board by melting a solder between each of the protruding electrodes and the terminals.
4 . The method according to claim 3 , wherein each of the protruding electrodes is a copper pillared bump electrode.
5 . The method, further comprising:
(d) after the step (c), disposing a plurality of solder balls on the lands of the wiring board and electrically connecting the solder balls to the lands, respectively.Join the waitlist — get patent alerts
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