Semiconductor apparatus

Abstract

A method for comparing phases between first and second clock signal includes the first clock signals to a first precharge circuit coupled between a first node and a first terminal to which a first voltage is applied. The first clock signal is supplied to a second precharge circuit coupled between a second node and the first terminal. The second clock signal is supplied to a first discharge circuit coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied. The second clock signal is supplied to a second discharge circuit coupled between the second node and the second terminal.

What is claimed is: 
     
         1 . A method for comparing the phases between a first clock signal and a second clock signal comprising:
 supplying the first clock signal to a first precharge circuit coupled between a first node and a first terminal to which a first voltage is applied, the first precharge circuit being configured to supply the first voltage to the first node when the first clock signal is in a first level;   supplying the first clock signal to a second precharge circuit coupled between a second node and the first terminal, the second precharge circuit being configured to supply the first voltage to the second node when the first clock signal is in the first level;   supplying the second clock signal to a first discharge circuit coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied, the first discharge circuit being configured to discharge the first node when the second clock signal is in a second level; and   supplying the second clock signal to a second discharge circuit coupled between the second node and the second terminal, the second discharge circuit being configured to discharge the second node when the second clock signal is in a third level.   
     
     
         2 . The method as claimed in  claim 1 , further comprising amplifying potentials between the first node and the second node. 
     
     
         3 . The method as claimed in  claim 2 , further comprising generating the first clock signal based on the result of the comparison of potentials. 
     
     
         4 . The method as claimed in  claim 1 , wherein amplitude of the first clock signal is greater than amplitude of the second clock signal. 
     
     
         5 . The method as claimed in  claim 1 , further comprising supplying the first clock signal to at least one of the first discharge circuit and the second discharge circuit. 
     
     
         6 . The method as claimed in  claims 5 , wherein the at least one of the first discharge circuit and the second discharge circuit includes a first transistor and a second transistor connected in series, the first clock signal being supplied to a gate of the first transistor and the second clock signal being supplied to a gate of the second transistor. 
     
     
         7 . The method as claimed in  claim 1 , further comprising supplying the first clock signal to a third precharge circuit coupled between the first node and the second node, the third precharge circuit being configured to electrically connect the first node to the second node when the first clock signal is in the first level. 
     
     
         8 . A device for comparing the phases between a first clock signal and a second clock signal comprising:
 a first precharge circuit to which the first clock signal is supplied and coupled between a first node and a first terminal to which a first voltage is applied, the first precharge circuit being configured to supply the first voltage to the first node when the first clock signal is in a first level;   a second precharge circuit to which the first clock signal is supplied and coupled between a second node and the first terminal, the second precharge circuit being configured to supply the first voltage to the second node when the first clock signal is in the first level;   a first discharge circuit to which the second clock signal is supplied and coupled between the first node and a second terminal to which a second voltage different from the first voltage is applied, the first discharge circuit being configured to discharge the first node when the second clock signal is in a second level; and   a second discharge circuit to which the second clock signal is supplied and coupled between the second node and the second terminal, the second discharge circuit being configured to discharge the second node when the second clock signal is in a third level.   
     
     
         9 . The device as claimed in  claim 8 , further comprising an amplifier for comparing potentials between the first node and the second node. 
     
     
         10 . The device as claimed in  claim 9 , further comprising a generator for generating the first clock signal based on the result of the comparison of potentials at the differential amplifier. 
     
     
         11 . The device as claimed in  claim 8 , wherein amplitude of the first clock signal is greater than amplitude of the second clock signal. 
     
     
         12 . The device as claimed in  claim 8 , wherein the first clock signal is supplied to at least one of the first discharge circuit and the second discharge circuit. 
     
     
         13 . The device as claimed in  claims 12 , wherein the at least one of the first discharge circuit and the second discharge circuit includes a first transistor and a second transistor connected in series, the first clock signal being supplied to a gate of the first transistor and the second clock signal being supplied to a gate of the second transistor. 
     
     
         14 . The device as claimed in  claim 8 , further comprising a third precharge circuit to which the first clock signal is supplied and coupled between the first node and the second node, the third precharge circuit being configured to electrically connect the first node to the second node when the first clock signal is in the first level. 
     
     
         15 . A method for comparing the phases between a first clock signal and a second clock signal comprising:
 supplying the first clock signal to a precharge circuit coupled between a first node and a second node, the precharge circuit being configured to electrically connect the first node and the second node when the first clock signal is in a first level;   supplying the second clock signal to a first discharge circuit coupled between the first node and a first terminal to which a first voltage is applied, the first discharge circuit being configured to discharge the first node when the second clock signal is in a second level; and   supplying the second clock signal to a second discharge circuit coupled between the second node and the first terminal, the second discharge circuit being configured to discharge the second node when the second clock signal is in a third level.   
     
     
         16 . The method as claimed in  claim 15 , further comprising amplifying potentials between the first node and the second node. 
     
     
         17 . The method as claimed in  claim 16 , further comprising generating the first clock signal based on the result of the comparison of potentials. 
     
     
         18 . The method as claimed in  claim 15 , wherein amplitude of the first clock signal is greater than amplitude of the second clock signal. 
     
     
         19 . The method as claimed in  claim 15 , further comprising supplying the first clock signal to at least one of the first discharge circuit and the second discharge circuit. 
     
     
         20 . The method as claimed in  claims 19 , wherein the at least one of the first discharge circuit and the second discharge circuit includes a first transistor and a second transistor connected in series, the first clock signal being supplied to a gate of the first transistor and the second clock signal being supplied to a gate of the second transistor.