Device performing refresh operations of memory areas

Abstract

Disclosed heroin is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.

1 . A method for refreshing a plurality of dynamic random access memory areas on a single chip comprising:
 receiving a first self-refresh command on a first channel;   generating a first refresh signal in response to the first self-refresh command and an oscillator signal;   refreshing a first memory area in response to the first refresh signal;   receiving a second self-refresh command on a second channel;   generating a second refresh signal in response to the second self-refresh command and the oscillator signal; and   refreshing a second memory area in response to the second refresh signal so as not to overlap with the refreshing of the first memory area.   
     
     
         2 . The method as claimed in  claim 1  wherein the first and second refresh signals are first and second refresh start signals. 
     
     
         3 . The method as claimed in  claim 1  further comprising generating first and second self-refresh entry signals in response to the first and second self-refresh commands. 
     
     
         4 . The method as claimed in  claim 1  wherein the first and second self-refresh commands are received asynchronously. 
     
     
         5 . The method as claimed in  claim 1  wherein the first and second refresh signals are generated by dividing the oscillator signal. 
     
     
         6 . The method as claimed in  claim 1  wherein the first and second refresh signals are generated by dividing the oscillator signal to provide a plurality of divided oscillator signals and decoding the divided oscillator signals. 
     
     
         7 . The method as claimed in  claim 1  wherein the first and second channels comprise through silicon vias. 
     
     
         8 . The method as claimed in  claim 1  further comprising:
 controlling a first oscillator in an operating state; 
 controlling a second oscillator in a halted state; and 
 selecting the first oscillator to provide the oscillator signal. 
 
     
     
         9 . The method as claimed in  claim 8  wherein the first oscillator is controlled in the operating state in response to a first fuse and the second oscillator is controlled in the halted state in response to a second fuse. 
     
     
         10 . The method as claimed in  claim 9  wherein the first and second fuses are laser fuses. 
     
     
         11 . The method as claimed in  claim 9  wherein the first and second fuses are electrical fuses. 
     
     
         12 . The method as claimed in  claim 8  wherein the first oscillator is controlled in the operating state and the second oscillator is controlled in the halted state in response to a register. 
     
     
         13 . The method as claimed in  claim 12  wherein the register is a volatile register. 
     
     
         14 . The method as claimed in  claim 12  wherein the register is a non-volatile register. 
     
     
         15 . A semiconductor device comprising:
 a plurality of dynamic random access memory areas formed on a single chip;   a first channel on which a first self-refresh command is received;   a first control circuit configured to generate a first refresh signal in response to the first self-refresh command and an oscillator signal and to refresh a first memory area in response to the first refresh signal;   a second channel on which a second self-refresh command is received;   a second control circuit configured to generate a second refresh signal in response to the second self-refresh command and the oscillator signal and to refresh a second memory area in response to the second refresh signal so as not to overlap with the refreshing of the first memory area.   
     
     
         16 . The semiconductor device as claimed in  claim 15  wherein the first and second refresh signals are first and second refresh start signals. 
     
     
         17 . The semiconductor device as claimed in  claim 15  wherein the first and second self-refresh commands are received asynchronously. 
     
     
         18 . The semiconductor device as claimed in  claim 15  wherein the first and second channels comprise through silicon vias. 
     
     
         19 . A method for refreshing a plurality of dynamic random access memory areas on a single chip comprising:
 receiving a first self-refresh command on a first channel, the first self-refresh command addressing a first memory area;   receiving a second self-refresh command on a second channel, the second self-refresh command addressing a second memory area; and   generating a reference signal for use in self-refresh operations in both the first memory area and the second memory area.   
     
     
         20 . The method as claimed in  claim 19 , further comprising temporally separating the refreshing of the first memory area from the refreshing of the second memory area by referring to the reference signal.