Semiconductor device and method of testing the same

Abstract

A semiconductor device includes a unit region including a circuit test region and a probe test region. The circuit test region includes a test circuit and a plurality of circuit test pads operatively coupled to the test circuit. The probe test region includes first and second probe test pads insulated from the circuit test pads, and a first resistance pattern operatively coupled to the first and second probe test pads.

What is claimed is: 
     
         1 . A method of testing a semiconductor device, comprising:
 establishing contact between a plurality of probe pins of a probe card and a first probe test pad and a second probe test pad disposed in a probe test region of the semiconductor device,   wherein the first and second probe test pads are operatively coupled to a first resistance pattern disposed in the probe test region, and are insulated from a plurality of circuit test pads disposed in a circuit test region of the semiconductor device; and   measuring a resistance value of the first resistance pattern.   
     
     
         2 . The method of  claim 1 , further comprising:
 establishing contact between the probe pins and the plurality of circuit test pads upon determining that the measured resistance value is within a tolerance of a real resistance value of the first resistance pattern.   
     
     
         3 . The method of  claim 1 , further comprising:
 inspecting the probe card upon determining that the measured resistance value is not within a tolerance of a real resistance value of the first resistance pattern.   
     
     
         4 . The method of  claim 1 , further comprising:
 measuring a resistance value of a second resistance pattern operatively coupled to the first probe test pad and a third probe test pad disposed in the probe test region after measuring the resistance value of the first resistance pattern,   wherein the third probe test pad is insulated from the circuit test pads.   
     
     
         5 . The method of  claim 1 , further comprising:
 measuring a resistance value of a second resistance pattern operatively coupled to a third probe test pad and a forth probe test pad disposed in the probe test region simultaneously with the first resistance value of the first resistance pattern,   wherein the third and fourth probe test pads are insulated from the circuit test pads and the first and second probe test pads.   
     
     
         6 . The method of  claim 1 , wherein the substrate includes a plurality of unit regions, and some of the unit regions include the test circuit region. 
     
     
         7 . The method of  claim 4 , wherein a resistance value between the second and third probe test pads is greater than the resistance value of the first resistance pattern. 
     
     
         8 . The method of  claim 4 , wherein the resistance value of the second resistance pattern and the resistance value of the first resistance pattern are substantially equal to each other. 
     
     
         9 . A method of testing a semiconductor device, comprising:
 preparing the semiconductor device including first and second probe test groups disposed in a probe test region and a plurality of circuit test pads disposed in a circuit test region,   wherein the first probe test group comprises a first probe test pad, a second probe test pad, a third probe test pad, a first resistance pattern, and a second resistance pattern,   wherein the first resistance pattern is operatively coupled to the first and second probe test pads, and the second resistance pattern is operatively coupled to the first and third probe test pads,   wherein the second probe test group comprises a fourth probe test pad, a fifth probe test pad, a sixth probe test pad, a third resistance pattern, and a fourth resistance pattern,   wherein the third resistance pattern is operatively coupled to the fourth and fifth probe test pads, and the fourth resistance pattern is operatively coupled to the fourth and sixth probe test pads, and   wherein the first and the second probe test groups are insulated from the plurality of circuit test pads;   measuring a resistance value of the first resistance pattern by contacting first and second probe pins of a probe card with the first and second probe test pads; and   measuring a resistance value of the third resistance pattern by contacting third and fourth probe pins of the probe card with the fourth and fifth probe test pads.   
     
     
         10 . The method of  claim 9 , wherein the first, second and third probe test pads are insulated from the fourth, fifth and sixth probe test pads. 
     
     
         11 . The method of  claim 9 , wherein the resistance value of the first resistance pattern and the resistance value of the third resistance pattern are simultaneously measured. 
     
     
         12 . The method of  claim 9 , further comprising:
 measuring a resistance value of the second resistance pattern by contacting the first and second probe pins with the first and third probe test pads after measuring the resistance value of the first resistance pattern; and   measuring a resistance value of the fourth resistance pattern by contacting the third and fourth probe pins with the fourth and sixth probe test pads after measuring the resistance value of the third resistance pattern.   
     
     
         13 . The method of  claim 9 , further comprising:
 establishing contact between the first, the second, the third and the fourth probe pins and the plurality of circuit test pads upon determining that the measured resistance values are within tolerances of real resistance values of the first and the second resistance patterns.   
     
     
         14 . The method of  claim 9 , further comprising:
 inspecting the probe card upon determining that the measured resistance values are not within tolerances of real resistance values of the first and the second resistance patterns.