Interconnect board and semiconductor device

Abstract

Impedance mismatching to be caused in signal transmission paths is reduced, without any restriction being put on the number of layers. An interconnect board according to an embodiment of the present technique includes: interconnect layers and insulating layers that are alternately stacked; vias that electrically connect the interconnect layers; front-surface-side electrode pads formed on the front-surface side; back-surface-side electrode pads that are formed on the back-surface side and are arranged in an array; and a conductor loop that is formed in a conductor path connecting one of the front-surface-side electrode pads and one of the back-surface-side electrode pads, the conductor loop being formed with interconnects in the interconnect layers and the vias, the conductor loop extending in a direction perpendicular to the thickness direction of the interconnect board.

1 . An interconnect board comprising:
 a plurality of interconnect layers and a plurality of insulating layers alternately stacked;   a plurality of vias electrically connecting the interconnect layers; a plurality of front-surface-side electrode pads formed on a front-surface side;   a plurality of back-surface-side electrode pads formed on a back-surface side and arranged in an array; and   a conductor loop formed in a conductor path connecting one of the front-surface-side electrode pads and one of the back-surface-side electrode pads, the conductor loop being formed with interconnects in the interconnect layers and the vias, the conductor loop extending in a direction perpendicular to a thickness direction of the interconnect board.   
     
     
         2 . The interconnect board according to  claim 1 , wherein one end of the conductor loop is located on the one of the back-surface-side electrode pads. 
     
     
         3 . The interconnect board according to  claim 1 , wherein an insertion member made of a different material from the material of the insulating layers is placed inside the conductor loop. 
     
     
         4 . The interconnect board according to  claim 3 , wherein a magnetic material is placed inside the conductor loop. 
     
     
         5 . The interconnect board according to  claim 1 , which is a coreless board. 
     
     
         6 . The interconnect board according to  claim 1 , wherein
 the conductor loop is formed for each conductor path in a pair of conductor paths for transmitting signals by a differential method, and   the conductor loops formed in the pair of the conductor paths have the opposite loop directions from each other between the front-surface-side electrode pads and the back-surface-side electrode pads.   
     
     
         7 . A semiconductor device comprising:
 an interconnect board including:
 a plurality of interconnect layers and a plurality of insulating layers alternately stacked; 
 a plurality of vias electrically connecting the interconnect layers; 
 a plurality of front-surface-side electrode pads formed on a front-surface side; 
 a plurality of back-surface-side electrode pads formed on a back-surface side and arranged in an array; and 
 a conductor loop formed in a conductor path connecting one of the front-surface-side electrode pads and one of the back-surface-side electrode pads, the conductor loop being formed with interconnects in the interconnect layers and the vias, the conductor loop extending in a direction perpendicular to a thickness direction of the interconnect board; and 
   a semiconductor electronic component electrically connected to the interconnect board via the front-surface-side electrode pads.