Densely packed standard cells for integrated circuit products, and methods of making same

Abstract

One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively

1 - 15 . (canceled) 
     
     
         16 . A transistor device, comprising:
 a gate structure;   a plurality of source/drain regions;   first and second unitary conductive source/drain contact structures, each of which contacts one of said plurality of source/drain regions; and   a via layer comprised of first and second conductive vias that contact said first and second unitary conductive source/drain contact structures, respectively.   
     
     
         17 . The device of  claim 16 , wherein said transistor is a FinFET transistor. 
     
     
         18 . The device of  claim 16 , further comprising a gate contact structure that is conductively coupled to said gate structure. 
     
     
         19 . The device of  claim 16 , wherein said via layer further comprises a third conductive via that is conductively coupled to said gate contact structure. 
     
     
         20 . The device of  claim 16 , wherein said first and second unitary conductive source/drain contact structures are positioned in a single layer of insulating material. 
     
     
         21 . A transistor device, comprising:
 a gate structure;   a plurality of source/drain regions;   first and second unitary conductive source/drain contact structures, each of which contacts one of said plurality of source/drain regions, wherein said first and second unitary conductive source/drain contact structures are positioned in a single layer of insulating material;   a via layer positioned above said single layer of insulating material, said via layer comprising first and second conductive vias that contact said first and second unitary conductive source/drain contact structures, respectively; and   a gate contact structure positioned in said single layer of insulating material, said gate contact structure being conductively coupled to said gate structure.   
     
     
         22 . The device of  claim 21 , wherein said transistor is a FinFET transistor. 
     
     
         23 . The device of  claim 21 , wherein said first and second unitary conductive source/drain contact structures each have an upper surface and a lower surface, wherein said upper surface of each of said first and second unitary conductive source/drain contact structures contacts a lower surface of said first and second conductive vias, respectively, and said lower surface of each of said first and second unitary conductive source/drain contact structures contacts one of said source/drain regions. 
     
     
         24 . The device of  claim 21 , wherein said via layer further comprises a third conductive via that is conductively coupled to said gate contact structure. 
     
     
         25 . The device of  claim 21 , wherein said first and second unitary conductive source/drain contact structures each have an upper surface and said gate contact structure has an upper surface, wherein said upper surfaces of said first and second unitary conductive source/drain contact structures and said upper surface of said gate contact structure lie in approximately the same plane. 
     
     
         26 . A transistor device, comprising:
 a gate structure;   a plurality of source/drain regions;   first and second unitary conductive source/drain contact structures, each of which has a bottom surface that contacts one of said plurality of source/drain regions; and   a via layer comprised of first and second conductive vias, each of which has a bottom surface that contacts an upper surface of said first and second unitary conductive source/drain contact structures, respectively; and   a gate contact structure that is conductively coupled to said gate structure, said gate contact structure having an upper surface, wherein said upper surfaces of said first and second unitary conductive source/drain contact structures and said upper surface of said gate contact structure lie in approximately the same plane.   
     
     
         27 . The device of  claim 26 , wherein said via layer further comprises a third conductive via that is conductively coupled to said gate contact structure. 
     
     
         28 . The device of  claim 26 , wherein said first and second unitary conductive source/drain contact structures are positioned in a single layer of insulating material. 
     
     
         29 . The device of  claim 28 , wherein said gate contact structure is positioned in said single layer of insulating material.